The Community for Technology Leaders
RSS Icon
Issue No.05 - Sept.-Oct. (2012 vol.9)
pp: 770-776
Xiaodao Chen , Michigan Technological University, Houghton
Chen Liao , Michigan Technological University, Houghton
Tongquan Wei , East China Normal University, Shanghai
Shiyan Hu , Michigan Technological University, Houghton
As VLSI technology enters the nanoscale regime, design reliability is becoming increasingly important. A major design reliability concern arises from electromigration which refers to the transport of material caused by ion movement in interconnects. Since the lifetime of an interconnect drastically depends on the current flowing through it, the electromigration problem aggravates with increasingly growing thinner wires. Further, the current-density-induced interconnect thermal issue becomes much more severe with larger current. To mitigate the electromigration and the current-density-induced thermal effects, interconnect current density needs to be reduced. Assigning wires to thick metals increases wire volume, and thus, reduces the current density. However, overstretching thick-metal assignment may hurt routability. Thus, it is highly desirable to minimize the thick-metal usage, or total wire cost, subject to the reliability constraint. In this paper, the minimum cost reliability-driven routing, which consists of Steiner tree construction and layer assignment, is considered. The problem is proven to be NP-hard and a highly effective iterative rounding-based integer linear programming algorithm is proposed. In addition, a unified routing technique is proposed to directly handle multiple current levels, which is critical in analog VLSI design. Further, the new algorithm is extended to handle blockage. Our experiments on 450 nets demonstrate that the new algorithm significantly outperforms the state-of-the-art work [CHECK END OF SENTENCE] with up to 14.7 percent wire reduction. In addition, the new algorithm can save 11.4 percent wires over a heuristic algorithm for handling multiple currents.
Routing, Wires, Driver circuits, Reliability, Steiner trees, Algorithm design and analysis, Current density, integer linear programming., VLSI circuit computer-aided design, interconnect reliability, electromigration, Steiner tree construction
Xiaodao Chen, Chen Liao, Tongquan Wei, Shiyan Hu, "An Interconnect Reliability-Driven Routing Technique for Electromigration Failure Avoidance", IEEE Transactions on Dependable and Secure Computing, vol.9, no. 5, pp. 770-776, Sept.-Oct. 2012, doi:10.1109/TDSC.2010.57
[1] J. Lienig and G. Jerke, "Current-Driven Wire Planning for Electromigration Avoidance in Analog Circuits," Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 783-788, 2003.
[2] J. Black, "Electromigration—A Brief Survey and Some Recent Results," Proc. IEEE Int'l Reliability Physics Symp., pp. 338-347, 1968.
[3] S. Hu, Z. Li, and C. Alpert, "A Polynomial Time Approximation Scheme for Timing Constrained Minimum Cost Layer Assignment," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 112-115, 2008.
[4] J. Lienig, G. Jerke, and T. Adler, "Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing," Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 372-380, 2002.
[5] G. Jerke, J. Lienig, and J. Scheible, "Reliability-Driven Layout Decompaction for Electromigration Failure Avoidance in Complex Mixed-Signal IC Designs," Proc. IEEE/ACM Design Automation Conf. (DAC), pp. 181-184, 2004.
[6] G. Jerke and J. Lienig, "Hierarchical Current Density Verification in Arbitrarily Shaped Metallization Patterns of Analog Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 80-90, Jan. 2004.
[7] G. Jerke and J. Lienig, "Hierarchical Current Density Verification for Electromigration Analysis in Arbitrarily Shaped Metallization Patterns of Analog Circuits," Proc. Design, Automation and Test in Europe (DATE) Conf. and Exhibition, pp. 464-469, 2002.
[8] J. Lienig, "Introduction to Electromigration-Aware Physical Design," Proc. Int'l Symp. Physical Design (ISPD), vol. 23, no. 1, pp. 80-90, 2004.
[9] M. Garey and D. Johnson, Computers and Intractability; A Guide to the Theory of NP-Completeness. W.H. Freeman, 1979.
[10] L. Behjat and A. Chiang, "Fast Integer Linear Programming Based Models for VLSI Global Routing," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), pp. 6238-6243, 2005.
[11] T. Terlaky, A. Vannelli, and H. Zhang, "On Routing in VLSI Design and Communication Networks," Discrete Applied Math., vol. 156, no. 11, pp. 2178-2194, 2008.
[12] S. Shah, A. Srivastava, D. Sharma, D. Sylvester, D. Blaauw, and V. Zolotov, "Discrete Vt Assignment and Gate Sizing Using a Self-Snapping Continuous Formulation," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 705-712, 2005.
4 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool