CSDL Home IEEE Transactions on Dependable and Secure Computing 2011 vol.8 Issue No.05 - September/October

Issue No.05 - September/October (2011 vol.8)

pp: 756-769

Yu Wang , Tsinghua University, Beijing

Hong Luo , Tsinghua University, Beijing

Ku He , Tsinghua University, Beijing

Rong Luo , Tsinghua University, Beijing

Huazhong Yang , Tsinghua University, Beijing

Yuan Xie , Pennsylvania State University, University Park

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2010.41

ABSTRACT

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.

INDEX TERMS

Negative bias temperature instability (NBTI), leakage reduction, temperature-aware NBTI modeling, circuit performance degradation.

CITATION

Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, "Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation",

*IEEE Transactions on Dependable and Secure Computing*, vol.8, no. 5, pp. 756-769, September/October 2011, doi:10.1109/TDSC.2010.41REFERENCES

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