Issue No. 01 - January-March (2010 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2008.31
Avi Timor , Technion Intel Corp., Haifa
Avi Mendelson , Technion Intel Corp., Haifa
Yitzhak Birk , Technion Intel Corp., Haifa
Neeraj Suri , TU Darmstadt, Darmstadt
Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft errors still occur infrequently, they are rapidly becoming a major impediment to processor reliability. This is due primarily to processor scaling characteristics. In the past, systems designed to tolerate such faults utilized costly customized solutions, entailing the use of replicated hardware components to detect and recover from microprocessor faults. As the feature size keeps shrinking and with the proliferation of multiprocessor on die in all segments of computer-based systems, the capability to detect and recover from faults is also desired for commodity hardware. For such systems, however, performance and power constitute the main drivers, so the traditional solutions prove inadequate and new approaches are required. We introduce two independent and complementary microarchitecture-level techniques: Double Execution and Double Decoding. Both exploit the typically low average processor resource utilization of modern processors to enhance processor reliability. Double Execution protects the Out-Of-Order part of the CPU by executing each instruction twice. Double Decoding uses a second, low-performance low-power instruction decoder to detect soft errors in the decoder logic. These simple-to-implement techniques are shown to improve the processor's reliability with relatively low performance, power, and hardware overheads. Finally, the resulting “excessive” reliability can even be traded back for performance by increasing clock rate and/or reducing voltage, thereby improving upon single execution approaches.
Transient faults, soft errors, superscalar, fault tolerance, microarchitecture, double execution.
N. Suri, A. Mendelson, A. Timor and Y. Birk, "Using Underutilized CPU Resources to Enhance Its Reliability," in IEEE Transactions on Dependable and Secure Computing, vol. 7, no. , pp. 94-109, 2008.