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Issue No.03 - July-September (2009 vol.6)
pp: 202-216
Radiation-induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft-error rates (SERs) in combinational circuits. In this work, we present methodologies to model soft errors in both the device and logic levels. At the device level, a hierarchical methodology to model neutron-induced soft errors is proposed. This model is used to create a transient current library, which will be useful for circuit-level soft-error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle, and location of impact. At the logic level, we propose a new approach to estimating the SER of logic circuits that attempts to capture electrical, logic, and latch window masking concurrently. The average error of the SER estimates using our approach, compared to the estimates obtained using circuit-level simulations, is 6.5 percent while providing an average speedup of 15,000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.
Soft errors, modeling, Soft-Error Analysis toolset, logic, device.
Rajaraman Ramanarayanan, Vijay Degalahal, Ramakrishnan Krishnan, Jung Sub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu, "Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits", IEEE Transactions on Dependable and Secure Computing, vol.6, no. 3, pp. 202-216, July-September 2009, doi:10.1109/TDSC.2007.70231
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