Issue No. 02 - April-June (2009 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2008.62
Alex Shye , Northwestern University, Evanston
Daniel A. Connors , University of Colorado, Boulder
Tipp Moseley , University of Colorado, Boulder
Joseph Blomstedt , University of Colorado, Boulder
Vijay Janapa Reddi , Harvard University, Cambridge
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point toward multicore designs, there is substantial interest in adapting such parallel hardware resources for transient fault tolerance. This paper presents process-level redundancy (PLR), a software technique for transient fault tolerance, which leverages multiple cores for low overhead. PLR creates a set of redundant processes per application process and systematically compares the processes to guarantee correct execution. Redundancy at the process level allows the operating system to freely schedule the processes across all available hardware resources. PLR uses a software-centric approach to transient fault tolerance, which shifts the focus from ensuring correct hardware execution to ensuring correct software execution. As a result, many benign faults that do not propagate to affect program correctness can be safely ignored. A real prototype is presented that is designed to be transparent to the application and can run on general-purpose single-threaded programs without modifications to the program, operating system, or underlying hardware. The system is evaluated for fault coverage and performance on a four-way SMP machine and provides improved performance over existing software transient fault tolerance techniques with a 16.9 percent overhead for fault detection on a set of optimized SPEC2000 binaries.
Fault tolerance, reliability, transient faults, soft errors, process-level redundancy.
Alex Shye, Daniel A. Connors, Tipp Moseley, Joseph Blomstedt, Vijay Janapa Reddi, "PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures", IEEE Transactions on Dependable and Secure Computing, vol. 6, no. , pp. 135-148, April-June 2009, doi:10.1109/TDSC.2008.62