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Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic functions for implementation on chip-cards. In this paper, a dynamic and differential look-up table (LUT) is presented and evaluated on a case study simulation. The proposed circuit shows a power consumption independent from the input data and can be employed to implement combinatorial functions in cryptographic processors when a high resistance against tampering is required. A typical application is the design of non-linear functions (e.g. substitution boxes) since protecting them with less expensive countermeasures (e.g. random masking) implies a significant overhead. In the adopted case study, a 1.02% spread in the power consumption has been obtained when parasitic capacitances are taken into account. Moreover, a comparison with a static CMOS implementation shows an acceptable overhead in terms of area and power consumption.
differential power analysis, DPA, power analysis, differential logic, dual rail logic, chip-cards, cryptography
M. Bucci, L. Giancane, R. Luzzi, A. Trifiletti, "A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards", IEEE Transactions on Dependable and Secure Computing, vol. 4, no. , pp. 245-251, October-December 2007, doi:10.1109/TDSC.2007.70212
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