CSDL Home IEEE Transactions on Dependable and Secure Computing 2005 vol.2 Issue No.04 - October-December
Issue No.04 - October-December (2005 vol.2)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2005.44
To achieve high reliability despite hard faults that occur during operation and to achieve high yield despite defects introduced at fabrication, a microprocessor must be able to tolerate hard faults. In this paper, we present a framework for autonomic self-repair of the array structures in microprocessors (e.g., reorder buffer, instruction window, etc.). The framework consists of three aspects: 1) detecting/diagnosing the fault, 2) recovering from the resultant error, and 3) mapping out the faulty portion of the array. For each aspect, we present design options. Based on this framework, we develop two particular schemes for self-repairing array structures (SRAS). Simulation results show that one of our SRAS schemes adds some performance overhead in the fault-free case, but that both of them mask hard faults 1) with less hardware overhead cost than higher-level redundancy (e.g., IBM mainframes) and 2) without the per-error performance penalty of existing low-cost techniques that combine error detection with pipeline flushes for backward error recovery (BER). When hard faults are present in arrays, due to operational faults or fabrication defects, SRAS schemes outperform BER due to not having to frequently flush the pipeline.
Index Terms- Logic design reliability and testing, microprocessors, and microcomputers.
Fred A. Bower, Sule Ozev, Daniel J. Sorin, "Autonomic Microprocessor Execution via Self-Repairing Arrays", IEEE Transactions on Dependable and Secure Computing, vol.2, no. 4, pp. 297-310, October-December 2005, doi:10.1109/TDSC.2005.44