Issue No. 09 - September (1995 vol. 17)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/34.406655
<p><it>Abstract</it>—Depth recovery from gray-scale images is an important topic in the field of computer and robot vision. Intensity gradient analysis (IGA) is a robust technique for inferring depth information from a sequence of images acquired by a sensor undergoing translational motion. IGA obviates the need for explicitly solving the correspondence problem and hence is an efficient technique for range estimation. Many applications require real time processing at very high frame rates. The design of special purpose hardware could significantly speed up the computations in IGA. In this paper, we propose two VLSI architectures for high-speed range estimation based on IGA. The architectures fully utilize the principles of pipelining and parallelism in order to obtain high speed and throughput. The designs are conceptually simple and suitable for implementation in VLSI.</p>
Range estimation, image processing, very large scale integration (VLSI) implementation, intensity gradient, systolic algorithm, special purpose architecture, hardware algorithm.
N. Ranganathan, Ramesh C. Jain, Raghu Sastry, "VLSI Architectures for High-Speed Range Estimation", IEEE Transactions on Pattern Analysis & Machine Intelligence, vol. 17, no. , pp. 894-899, September 1995, doi:10.1109/34.406655