Issue No. 08 - August (1995 vol. 17)

ISSN: 0162-8828

pp: 824-830

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/34.400575

ABSTRACT

<p><it>Abstract</it>—The edit distance between two strings <it>a</it><sub>1</sub>, …, <it>a</it><sub><it>m</it></sub> and <it>b</it><sub>1</sub>, …, <it>b</it><sub><it>n</it></sub> is the minimum cost <it>s</it> of a sequence of editing operations (insertions, deletions and substitutions) that convert one string into the other. This paper describes the design and implementation of a linear systolic array chip for computing the edit distance between two strings over a given alphabet. An encoding scheme is proposed which reduces the number of bits required to represent a state in the computation. The architecture is a parallel realization of the standard dynamic programming algorithm proposed by Wagner and Fischer, and can perform approximate string matching for variable edit costs. More importantly, the architecture does not place any constraint on the lengths of the strings that can be compared. It makes use of simple basic cells and requires regular nearest-neighbor communication, which makes it suitable for VLSI implementation. A prototype of this array has been built at the University of South Florida.</p>

INDEX TERMS

Edit distance computation, string-to-string correction problem, very large scale integration (VLSI) implementation, systolic algorithm, special purpose architecture, hardware algorithm.

CITATION

Raghu Sastry, N. Ranganathan, Klinton Remedios, "CASM: A VLSI Chip for Approximate String Matching",

*IEEE Transactions on Pattern Analysis & Machine Intelligence*, vol. 17, no. , pp. 824-830, August 1995, doi:10.1109/34.400575