Issue No. 08 - August (1992 vol. 14)

ISSN: 0162-8828

pp: 857-865

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/34.149596

ABSTRACT

<p>The discrete relaxation algorithm (DRA) is a computational technique that enforces arc consistency (AC) in a constraint satisfaction problem (CSP). The original sequential AC-1 algorithm suffers from O(n/sup 3/m/sup 3/) time complexity, and even the optimal sequential AC-4 algorithm is O(n/sup 2/m/sup 2/) for an n-object and m-label DRA problem. Sample problem runs show that these algorithms are all too slow to meet the need for any useful, real-time CSP applications. A parallel DRA5 algorithm that reaches a lower bound of O(nm) (where the number of processors is polynomial in the problem size) is given. A fine-grained, massively parallel hardware computer architecture has been designed for the DRA5 algorithm. For practical problems, many orders of magnitude of efficiency improvement can be reached on such a hardware architecture.</p>

INDEX TERMS

discrete relaxation algorithm; sequential AC-1 algorithm; time complexity; sequential AC-4 algorithm; parallel DRA5 algorithm; polynomial; computational complexity; parallel algorithms; parallel architectures; polynomials

CITATION

J. Gu, W. Wang, "A Novel Discrete Relaxation Architecture",

*IEEE Transactions on Pattern Analysis & Machine Intelligence*, vol. 14, no. , pp. 857-865, August 1992, doi:10.1109/34.149596