Issue No. 03 - July-September (1998 vol. 4)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2945.722301
<p><b>Abstract</b>—Recently, SIMD processors have become popular architectures for multimedia. Though most of the 3D graphics pipeline can be implemented on such SIMD platforms in a straightforward manner, polygon clipping tends to cause clumsy and expensive interruptions to the SIMD pipeline. This paper describes a way to increase the efficiency of SIMD clipping without sacrificing the efficient flow of a SIMD graphics pipeline. In order to fully utilize the parallel execution units, we have developed two methods to avoid serialization of the execution stream: <it>Deferred clipping</it> postpones polygon clipping and uses hardware assistance to buffer polygons that need to be clipped. <it>SIMD Clipping</it> partitions the actual polygon clipping procedure between the SIMD engine and a conventional RISC processor. To increase the efficiency of SIMD clipping, we introduce the concepts of clip-plane pairs and edge batching. Clip-plane pairs allow clipping a polygon against two clip planes without introducing corner vertices. Edge batching reduces the communication and control overhead for starting of clipping on the SIMD engine.</p>
Polygon clipping, single-instruction multiple-data (SIMD) computer, deferred clipping, perspective projection, clip-plane pairs, edge batching.
B. Schneider and J. van Welzen, "Efficient Polygon Clipping for an SIMD Graphics Pipeline," in IEEE Transactions on Visualization & Computer Graphics, vol. 4, no. , pp. 272-285, 1998.