Issue No. 02 - Feb. (2015 vol. 26)
Alexander Shpiner , Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, Israel
Erez Kantor , CSAIL, MIT, Cambridge, MA
Pu Li , ASML, Netherlands, B.V.
Israel Cidon , Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, Israel
Isaac Keslassy , Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, Israel
Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In particular, bufferless NoCs require significantly less area and power consumption, but also pose novel major scheduling problems to achieve full capacity. In this paper, we provide first insights on the capacity of bufferless NoCs. In particular, we present
optimal periodic schedules for several bufferless NoCs with a complete-exchange traffic pattern. These schedules particularly fit distributed-programming models and network congestion-control mechanisms. In addition, for general traffic patterns, we also introduce efficient greedy scheduling algorithms, that often outperform simple greedy online algorithms and cannot have deadlocks. Finally, using network simulations, we quantify the speedup of our suggested algorithms, and show how they improve throughput by up to 35 percent on a torus network.
Schedules, Topology, Network topology, Routing, Optimal scheduling, Scheduling, Algorithm design and analysis
A. Shpiner, E. Kantor, P. Li, I. Cidon and I. Keslassy, "On the Capacity of Bufferless Networks-on-Chip," in IEEE Transactions on Parallel & Distributed Systems, vol. 26, no. 2, pp. 492-506, 2015.