Issue No. 05 - May (2014 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2013.261
Thilan Ganegedara , Department of Electrical Engineering, University of Southern California, Los Angeles, CA, USA
Weirong Jiang , Xilinx Research Labs, San Jose, USA
Viktor K. Prasanna , Department of Electrical Engineering, University of Southern California , Los Angeles, CA, USA
Packet classification is widely used as a core function for various applications in network infrastructure. With increasing demands in throughput, performing wire-speed packet classification has become challenging. Also the performance of today's packet classification solutions depends on the characteristics of rulesets. In this work, we propose a novel modular Bit-Vector (BV) based architecture to perform high-speed packet classification on Field Programmable Gate Array (FPGA). We introduce an algorithm named StrideBV and modularize the BV architecture to achieve better scalability than traditional BV methods. Further, we incorporate range search in our architecture to eliminate ruleset expansion caused by range-to-prefix conversion. The post place-and-route results of our implementation on a state-of-the-art FPGA show that the proposed architecture is able to operate at 100+ Gbps for minimum size packets while supporting large rulesets up to 28 K rules using only the on-chip memory resources. Our solution is ruleset-feature independent , i.e. the above performance can be guaranteed for any ruleset regardless the composition of the ruleset.
Pipelines, Field programmable gate arrays, Hardware, Throughput, Memory management, Arrays, Vectors
T. Ganegedara, W. Jiang and V. K. Prasanna, "A Scalable and Modular Architecture for High-Performance Packet Classification," in IEEE Transactions on Parallel & Distributed Systems, vol. 25, no. 5, pp. 1135-1144, 2014.