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Issue No. 04 - April (2014 vol. 25)
ISSN: 1045-9219
pp: 929-938
Wu Jigang , Sch. of Comput. Sci. & Software Eng., Tianjin Polytech. Univ., Tianjin, China
Thambipillai Srikanthan , Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
Guiyuan Jiang , Sch. of Comput. Sci. & Technol., Tianjin Univ., Tianjin, China
Kai Wang , Sch. of Software & Microelectron., Peking Univ., Beijing, China
Reducing the interconnection length of VLSI arrays leads to less capacitance, power dissipation and dynamic communication cost between the processing elements (PEs). This paper develops efficient algorithms for constructing tightly-coupled subarrays from the mesh-connected VLSI arrays with faulty PEs. For a given size r·s of the target (logical) array, the proposed algorithm searches and reroutes a physical r×s subarray that has the least number of faults, resulting in an approximate target array, which is subsequently extended to the desired target array. Experimental results show that over 65 percent redundant interconnects can be reduced for a 64×64 target array on the 512×512 host array with no more than 1 percent faults. In addition, we propose a recursive divide-and-conquer algorithm for constructing the maximum target array (MTA). The lower bound of the total interconnection length of the MTA has been established. Experimental results show that the proposed algorithm is capable of reducing the long interconnects by over 33 percent for the MTA derived from the 512×512 host array with no more than 1 percent faults. Moreover, the proposed total interconnection length of target array is close to the lower bound for the cases with relatively fewer number of faults.
Logic arrays, Switches, Very large scale integration, Computer architecture, Circuit faults, Fault tolerance, Fault tolerant systems

Wu Jigang, T. Srikanthan, Guiyuan Jiang and Kai Wang, "Constructing Sub-Arrays with ShortInterconnects from Degradable VLSI Arrays," in IEEE Transactions on Parallel & Distributed Systems, vol. 25, no. 4, pp. 929-938, 2014.
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