Issue No. 04 - April (2014 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2013.104
Emmanuel Jeannot , INRIA Bordeaux Sud-Ouest, Talence, France
Guillaume Mercier , INRIA Bordeaux Sud-Ouest, Talence, France
Francois Tessier , INRIA Bordeaux Sud-Ouest, Talence, France
Current generations of NUMA node clusters feature multicore or manycore processors. Programming such architectures efficiently is a challenge because numerous hardware characteristics have to be taken into account, especially the memory hierarchy. One appealing idea to improve the performance of parallel applications is to decrease their communication costs by matching the communication pattern to the underlying hardware architecture. In this paper, we detail the algorithm and techniques proposed to achieve such a result: first, we gather both the communication pattern information and the hardware details. Then we compute a relevant reordering of the various process ranks of the application. Finally, those new ranks are used to reduce the communication costs of the application.
Hardware, Topology, Computational modeling, Network topology, Multicore processing, Standards
E. Jeannot, G. Mercier and F. Tessier, "Process Placement in Multicore Clusters:Algorithmic Issues and Practical Techniques," in IEEE Transactions on Parallel & Distributed Systems, vol. 25, no. 4, pp. 993-1002, 2014.