The Community for Technology Leaders
RSS Icon
Issue No.10 - Oct. (2013 vol.24)
pp: 2109-2120
Kun-Chih Chen , National Taiwan University, Taipei
Shu-Yen Lin , National Taiwan University, Taipei
Hui-Shun Hung , National Taiwan University, Taipei
An-Yeu Andy Wu , National Taiwan University, Taipei
Three-dimensional network-on-chip (3D NoC) has been proposed to solve the complex on-chip communication issues in future 3D multicore systems. However, the thermal problems of 3D NoC are more serious than 2D NoC due to chip stacking. To keep the temperature below a certain thermal limit, the thermal emergent routers are usually throttled. Then, the topology of 3D NoC becomes a Nonstationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, some routing algorithms had been proposed in the previous works. However, the network still suffers from extremely traffic imbalance among lateral and vertical logic layer. In this paper, we propose a Topology Aware Adaptive Routing (TAAR) to balance the traffic load for NSI-Mesh in 3D NoC. TAAR has three routing modes, which can be dynamically adjusted based on the topology status of the routing path. In addition to increasing routing flexibility, the TAAR also increases both vertical and lateral path diversity to balance the traffic load. Compared with the related adaptive routing methods, the experimental results show that the proposed TAAR can reduce 19 to 295 percent traffic loads in the bottom logic layer and improve around 7.7 to 380 percent network throughput. According to our proposed VLSI architecture, the TAAR only needs less than 24.8 percent hardware overhead compared with the previous works.
Routing, Topology, Network topology, Telecommunication traffic, Nickel, System recovery, Complexity theory, transport layer assisted routing, Network-on-chip, 3D IC, 3D NoC
Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung, An-Yeu Andy Wu, "Topology-Aware Adaptive Routing for Nonstationary Irregular Mesh in Throttled 3D NoC Systems", IEEE Transactions on Parallel & Distributed Systems, vol.24, no. 10, pp. 2109-2120, Oct. 2013, doi:10.1109/TPDS.2012.291
[1] S. Kumar et al., "A Network on Chip Architecture and Design Methodology," Proc. Int'l Symp. Very Large Scale Integration, pp. 105-112, 2002.
[2] Y. Jin et al., "Communication-Aware Globally-Coordibated On-Chip Networks," IEEE Trans. Parallel and Distributes Systems, vol. 23, no. 2, pp. 242-254, Feb. 2012.
[3] R. Marculescu et al., "Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3-21, Jan. 2009.
[4] A.W. Topol et al., "Three-Dimensional Integrated Circuits," IBM J. Research Development, vol. 50, no. 4/5, pp. 491-506, 2006.
[5] B.S. Feero and P.P. Pande, "Networks-On-Chip in a Three Dimensional Environment: A Performance Evaluation," IEEE Trans. Computers, vol. 58, no. 1, pp. 32-45, Jan. 2009.
[6] Mobile Intel Pentium 4 Processor - M Datasheet, http:/, 2013.
[7] L. Shang et al., "Thermal Modeling, Characterization and Management of On-Chip Networks," Proc. IEEE/ACM Int'l Symp. Microarchitecture (Micro), pp. 67-68, Dec. 2004.
[8] K. Lahiri et al., "Performance Analysis of Systems with Multi-Channel Communication," Proc. Int'l Conf. VLSI Design, pp. 530-537, 2000.
[9] K.Y. Jheng et al., "Traffic-Thermal Mutual-Coupling Co-Simulation Platform for Three-Dimensional Network-on-Chip," Proc. IEEE Int'l Symp. VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2010.
[10] C.H. Chao et al., "Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC System," Proc. IEEE Int'l Symp. Network-on-Chip (NOCS), pp. 223-230, May 2010.
[11] C.H. Chao et al., "Transport Layer Assisted Routing for Non-Stationary Irregular Mesh of Thermal-Aware 3D Network-on-Chip Systems," Proc. IEEE Int'l SOC Conf. (SOCC), Sept. 2011.
[12] M.K.F. Schafer et al., "Deadlock-Free Routing and COmpinent Placement for Irregular Mesh-Based Network-on-Chip," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 238-245, 2005.
[13] R. Holsmark and S. Kumar, "Design Issues and Performance Evaluation of Mesh NoC with Regions," Proc. Norchip Conf., pp. 40-43, 2005.
[14] S.Y. Lin et al., "Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks," IEEE Trans. Computers, vol. 57, no. 9, pp. 1156-1168, Sept. 2008.
[15] P. Mahdavinia et al., "An Efficient Routing Algorithm for Irregular Mesh NoCs," Proc. IEEE Int'l Symp. Circuit and System (ISCAS), 2010.
[16] S.Y. Lin et al., "Traffic-and Thermal-Aware Routing for Throttling Three-Dimensional Network-on-Chip System," Proc. IEEE Int'l Symp. VLSI Design, Automation, and Test (VLSI-DAT), pp. 135-138, Apr. 2011.
[17] C.H. Chao et al., "Transport Layer Assisted Routing for Run-Time Thermal Management of 3D NoC Systems," to be Appeared in, ACM Trans. Embedded Computing Systems.
[18] G.M. Chiu, "The Odd-Even Turn Model for Adaptive Routing," IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July 2000.
[19] P. Gratz et al., "Regional Congestion Awareness for Load Balance in Network-on-Chip," Proc. IEEE Symp. High Performance Computer Architecture (HPCA), pp. 203-214, Feb. 2008.
[20] L.G. Valiant, "A Scheme for Fast Parallel Communication," SIAM J. Computing, vol. 11, pp. 350-361, 1982.
[21] T. Nesson and S.L. Johnsson, "ROMM Routing on Mesh and Torus Networks," Proc. ACM Symp. Parallel Algorithms and Architectures (SPAA), 1995.
[22] A. Singh et al., "GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks," Proc. Int'l Symp. Computer Architecture (ISCA), 2003.
[23] G. Ascia et al., "Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Network-on-Chip," IEEE Trans. Computers, vol. 57, no. 6, pp. 809-820, June 2008.
[24] G. Ascia et al., "Neighbors-on-Path: A New Selections Strategy for on-Chip-Networks," Proc. IEEE/ACM/IFIP Workshop Embedded Systems for Real Time Multimedia, Oct. 2006.
[25] J. Hu and R. Marculescu, "Application-Specific Buffer Space Allocation for Networks-on-Chip Router Design," Proc. IEEE/ACM Int'l Conf. Computer Aided Design (ICCAD), pp. 354-361, Nov. 2004.
[26] Noxim:, 2013.
[27] W. Huang et al., "HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design," IEEE Trans. Very Large Scale Integrated Systems, vol. 14, no. 5, pp. 501-513, May 2006.
[28] Y. Hoskote, "A 5-GHz Mesh Interconnect for a Teraflops Processor," IEEE Micro, vol. 27, no. 5, pp. 51-61, Sept./Oct. 2007.
[29] X. Wang et al., "Adaptive Power Control with Online Model Estimation for Chip Multiprocessors," IEEE Trans. Parallel and Distributed Systems, vol. 22, no. 10, pp. 1681-1696, Oct. 2011.
[30] A. Bartolini et al., "Thermal and Energy Management of High-Performance Multicores: Distributed and Self-Calibrating Model-Predictive Controller," IEEE Trans. Parallel and Distributed Systems, vol. 24, no. 1, pp. 170-183, Jan. 2013.
[31] A. Jankes et al., "Benefits of Selective Packet Discard in Networks-on-Chip," ACM Trans. Architecture Code Optimization, vol. 9, no. 2,article 12, 2012.
[32] http://www.ieee802.org11/, 2013.
[33], 2013.
[34] C. Cardo et al., "A Flexible NoC-Based LDPC Code Decoder Implementation and Bandwidth Reduction Methods," Proc. Conf. Design and Architecture for Signal and Image Processing (DASIP), pp. 1-8, Nov. 2011.
[35] W.H. Hu et al., "Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform," Proc. Int'l Symp. Computer Architecture High Performance Computers (SBAC-PAD), pp. 35-40, Oct. 2009.
[36] J. Flich and J. Duato, "Logic-Based Distributed Routing for NoCs," IEEE Computer Architecture Letters, vol. 7, no. 1, pp. 13-16, June 2008.
[37] S.C. Woo et al., "The Splash-2 Programs: Characterization and Methodological Considerations," Proc. Int'l Symp. Computer Architecture, pp. 24-36, 1995.
[38] J.H. Bahn et al., "Parallel FFT Algorithms on Network-on-Chips," Proc. Int'l Conf. Information Technology: New Generations (ITNG), pp. 1087-1093, 2008.
9 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool