Issue No. 08 - Aug. (2012 vol. 23)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2011.304
José L. Abellán , University of Murcia, Murcia
Juan Fernández , Intel Barcelona Research Center, Intel Labs, Universitat Politècnica de Catalunya, Barcelona
Manuel E. Acacio , Universidad de Murcia, Murcia
Traditional software-based barrier implementations for shared memory parallel machines tend to produce hotspots in terms of memory and network contention as the number of processors increases. This could limit their applicability to future many-core CMPs in which possibly several dozens of cores would need to be synchronized efficiently. In this work, we develop GBarrier, a hardware-based barrier mechanism especially aimed at providing efficient barriers in future many-core CMPs. Our proposal deploys a dedicated G-line-based network to allow for fast and efficient signaling of barrier arrival and departure. Since GBarrier does not have any influence on the memory system, we avoid all coherence activity and barrier-related network traffic that traditional approaches introduce and that restrict scalability. Through detailed simulations of a 32-core CMP, we compare GBarrier against one of the most efficient software-based barrier implementations for a set of kernels and scientific applications. Evaluation results show average reductions of 54 and 21 percent in execution time, 53 and 18 percent in network traffic, and also 76 and 31 percent in the energy-delay² product metric for the full CMP when the kernels and scientific applications, respectively, are considered.
Many-core CMPs, barrier synchronization, global lines, S-CSMA, cache coherence, scalability, energy efficiency.
M. E. Acacio, J. Fernández and J. L. Abellán, "Efficient Hardware Barrier Synchronization in Many-Core CMPs," in IEEE Transactions on Parallel & Distributed Systems, vol. 23, no. , pp. 1453-1466, 2011.