Issue No. 08 - Aug. (2012 vol. 23)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2011.255
Rafael Ubal , Northeastern University, Boston
Julio Sahuquillo , Universidad Politécnica de Valencia, Valencia
Salvador Petit , Universidad Politécnica de Valencia, Valencia
Pedro López , Universidad Politécnica de Valencia, Valencia
David R. Kaeli , Northeastern University, Boston
Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking effects in the reorder buffer (ROB). Expanding the width of the instruction window can be highly beneficial to multiprocessors that implement a strict memory model, especially when both loads and stores encounter long latencies due to cache misses, and whose stalls must be overlapped with instruction execution to overcome the memory latencies. Based on the Validation Buffer (VB) architecture (a previously proposed out-of-order retirement, checkpoint-free architecture for single processors), this paper proposes a cost-effective, scalable, out-of-order retirement multiprocessor, capable of enforcing sequential consistency without impacting the design of the memory hierarchy or interconnect. Our simulation results indicate that utilizing a VB can speed up both relaxed and sequentially consistent in-order retirement in future multiprocessor systems by between 3 and 20 percent, depending on the ROB size.
Out-of-order retirement, multicore processors, validation buffer, sequential consistency.
D. R. Kaeli, P. López, S. Petit, R. Ubal and J. Sahuquillo, "A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions," in IEEE Transactions on Parallel & Distributed Systems, vol. 23, no. , pp. 1361-1368, 2011.