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Issue No.10 - Oct. (2011 vol.22)
pp: 1681-1696
Xiaorui Wang , The Ohio State University, Columbus
Kai Ma , The Ohio State University, Columbus
Yefu Wang , University of Tennessee, Knoxville, Knoxville
As chip multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while controlling the power or temperature of a CMP chip to stay below a constraint. The availability of per-core dynamic voltage and frequency scaling (DVFS) also makes it possible to develop advanced management strategies. However, most existing solutions rely on open-loop search or optimization with the assumption that power can be estimated accurately, while others adopt oversimplified feedback control strategies to control power and temperature separately, without any theoretical guarantees. In this paper, we propose a chip-level power control algorithm that is systematically designed based on optimal control theory. Our algorithm can precisely control the power of a CMP chip to the desired set point while maintaining the temperature of each core below a specified threshold. Furthermore, an online model estimator is designed to achieve analytical assurance of control accuracy and system stability, even in the face of significant workload variations or unpredictable chip or core variations. To further improve system performance, we also integrate dynamic cache resizing into our control framework so that power can be shifted among CPU cores and the shared L2 cache. Empirical results on a physical testbed show that our controller outperforms two state-of-the-art control algorithms by having better SPEC benchmark performance and more precise power control. In addition, extensive simulation results demonstrate the efficacy of our algorithm for various CMP configurations.
Power control, power capping, chip multiprocessor, cache resizing, feedback control, online model estimation.
Xiaorui Wang, Kai Ma, Yefu Wang, "Adaptive Power Control with Online Model Estimation for Chip Multiprocessors", IEEE Transactions on Parallel & Distributed Systems, vol.22, no. 10, pp. 1681-1696, Oct. 2011, doi:10.1109/TPDS.2011.39
[1] D. Brooks et al., "Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors," IEEE Micro, vol. 27, no. 3, pp. 49-62, May/June 2007.
[2] D. Brooks and M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors," Proc. Seventh Int'l Symp. High-Performance Computer Architecture (HPCA), 2001.
[3] D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA), 2000.
[4] J. Chang and G.S. Sohi, "Cooperative Cache Partitioning for Chip Multiprocessors," Proc. 21st Ann. Int'l Conf. Supercomputing (ICS '07), 2007.
[5] Y. Chen, A. Das, W. Qin, A. Sivasubramaniam, Q. Wang, and N. Gautam, "Managing Server Energy and Operational Costs in Hosting Centers," ACM SIGMETRICS Performance Evaluation Rev., vol. 33, no. 1, pp. 303-314, 2005.
[6] J. Donald and M. Martonosi, "Techniques for Multicore Thermal Management: Classification and New Exploration," Proc. 33rd Ann. Int'l Symp. Computer Architecture (ISCA '06), 2006.
[7] S. Eyerman, L. Eeckhout, T. Karkhanis, and J.E. Smith, "A Performance Counter Architecture for Computing Accurate CPI Components," ACM SIGOPS Operating Systems Rev., vol. 40, no. 5, 2006.
[8] M.E. Femal and V.W. Freeh, "Boosting Data Center Performance through Non-Uniform Power Allocation," Proc. Second Int'l Conf. Autonomic Computing (ICAC), 2005.
[9] G.F. Franklin, J.D. Powell, and M. Workman, Digital Control of Dynamic Systems, third ed. Addition-Wesley, 1997.
[10] Y. Han et al., "TILTS: A Fast Architectural-Level Transient Thermal Simulation Method," J. Low Power Electronics, vol. 3, no. 1, pp. 13-21, 2007.
[11] T. Horvath, T. Abdelzaher, K. Skadron, and X. Liu, "Dynamic Voltage Scaling in Multi-Tier Web Servers with End-to-End Delay Control," IEEE Trans. Computers, vol. 56, no. 4, pp. 444-458, Apr. 2007.
[12] C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi, "An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-39), 2006.
[13] C. Isci and M. Martonosi, "Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data," Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-36), 2003.
[14] T.A. Johansen, W. Jackson, R. Schreiber, and P. Tondel, "Hardware Synthesis of Explicit Model Predictive Controllers," IEEE Trans. Control Systems Technology, vol. 15, no. 1, pp. 191-197, Jan. 2007.
[15] J.O. Kephart, H. Chan, R. Das, D.W. Levine, G. Tesauro, F. Rawson, and C. Lefurgy, "Coordinating Multiple Autonomic Managers to Achieve Specified Power-Performance Tradeoffs," Proc. Fourth Int'l Conf. Autonomic Computing (ICAC '07), 2007.
[16] W. Kim et al., "System Level Analysis of Fast, Per-Core DVFS Using On-Chip Switching Regulators," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA), 2008.
[17] P.R. Kumar, "Convergence of Adaptive Control Schemes Using Least-Squares Parameter Estimates," IEEE Trans. Automatic Control, vol. 35, no. 4, pp. 416-424, Apr. 1990.
[18] D. Kusic, J. Kephart, J. Hanson, N. Kandasamy, and G. Jiang, "Power and Performance Management of Virtualized Computing Environments via Lookahead Control," Proc. Int'l Conf. Autonomic Computing (ICAC '08), 2008.
[19] C. Lefurgy, X. Wang, and M. Ware, "Server-Level Power Control," Proc. Fourth Int'l Conf. Autonomic Computing (ICAC '07), 2007.
[20] F.L. Lewis and V.L. Syrmos, Optimal Control, second ed. John Wiley & Sons, Inc., 1995.
[21] X. Liu et al., "Optimal Multivariate Control for Differentiated Services on a Shared Hosting Platform," Proc. IEEE 46th Conf. Decision and Control (CDC), 2007.
[22] J.M. Maciejowski, Predictive Control with Constraints. Prentice Hall, 2002.
[23] R. McGowen et al., "Power and Temperature Control on a 90-nm Itanium Family Processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 229-237, Jan. 2006.
[24] K. Meng, R. Joseph, R.P. Dick, and L. Shang, "Multi-Optimization Power Management for Chip Multiprocessors," Proc. 17th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT '08), 2008.
[25] R.J. Minerick, V.W. Freeh, and P.M. Kogge, "Dynamic Power Management Using Feedback," Proc. Workshop Compilers and Operating Systems for Low Power (COLP), 2002.
[26] U.Y. Ogras, R. Marculescu, and D. Marculescu, "Variation-Adaptive Feedback Control for Networks-on-Chip with Multiple Clock Domains," Proc. 45th Ann. Design Automation Conf. (DAC '08), 2008.
[27] M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T.N. Vijaykumar, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '00), 2000.
[28] M.K. Qureshi and Y.N. Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-39), 2006.
[29] R. Raghavendra, P. Ranganathan, V. Talwar, Z. Wang, and X. Zhu, "No Power Struggles: Coordinated Multi-Level Power Management for the Data Center," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2008.
[30] P. Ranganathan, P. Leech, D. Irwin, and J.S. Chase, "Ensemble-Level Power Management for Dense Blade Servers," Proc. 33rd Ann. Int'l Symp. Computer Architecture (ISCA '06), 2006.
[31] V. Sharma, A. Thomas, T. Abdelzaher, K. Skadron, and Z. Lu, "Power-Aware QoS Management in Web Servers," Proc. 24th IEEE Int'l Real-Time Systems Symp. (RTSS), 2003.
[32] K. Skadron, T. Abdelzaher, and M.R. Stan, "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management," Proc. Eighth Int'l Symp. High-Performance Computer Architecture (HPCA '02), 2002.
[33] K. Skadron et al., "Temperature-Aware Microarchitecture: Modeling and Implementation," ACM Trans. Architecture and Code Optimization, vol. 1, no. 1, pp. 1-32, 2004.
[34] S. Srikantaiah, M. Kandemir, and Q. Wang, "Sharp Control: Controlled Shared Cache Management in Chip Multiprocessors," Proc. 42nd Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-42), 2009.
[35] R. Teodorescu and J. Torrellas, "Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors," Proc. 35th Ann. Int'l Symp. Computer Architecture (ISCA '08), 2008.
[36] X. Wang and M. Chen, "Cluster-Level Feedback Power Control for Performance Optimization," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA '08), 2008.
[37] X. Wang, M. Chen, C. Lefurgy, and T.W. Keller, "Ship: Scalable Hierarchical Power Control for Large-Scale Data Centers," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques (PACT '09), 2009.
[38] X. Wang, K. Ma, and Y. Wang, "Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors," Proc. 39th Int'l Conf. Parallel Processing (ICPP), 2010.
[39] Y. Wang, K. Ma, and X. Wang, "Temperature-Constrained Power Control for Chip Multiprocessors with Online Model Estimation," Proc. 36th Int'l Symp. Computer Architecture (ISCA '09), 2009.
[40] M. Ware et al., "Architecting for Power Management: The IBM POWER7 Approach," Proc. IEEE 16th Int'l Symp. High-Performance Computer Architecture (HPCA), 2010.
[41] S.J.E. Wilton and N.P. Jouppi, "Cacti: An Enhanced Cache Access and Cycle Time Model," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 677-688 , May 1996.
[42] W. Wu, L. Jin, J. Yang, P. Liu, and S.X.-D. Tan, "A Systematic Method for Functional Unit Power Estimation in Microprocessors," Proc. 43rd Ann. Design Automation Conf. (DAC '06), 2006.
[43] Y. Zhang et al., "Hotleakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects," Technical Report CS-2003-05, Univ. of Virginia, 2003.
[44] C. Zhu, Z.P. Gu, L. Shang, R.P. Dick, and R. Joseph, "Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1479-1492, Aug. 2008.
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