Issue No. 07 - July (2011 vol. 22)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2010.196
Atef Ibrahim , Electronics Research Institute, Cairo
Fayez Gebali , University of Victoria, Victoria
Hamed Elsimary , Electronics Research Institute, Cairo
Amin Nassar , Cairo University, Cairo
This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.
Processor array, Montgomery multiplication, scalability, cryptography, secure communications, low power modular multipliers.
F. Gebali, A. Nassar, H. Elsimary and A. Ibrahim, "Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm," in IEEE Transactions on Parallel & Distributed Systems, vol. 22, no. , pp. 1142-1149, 2010.