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Issue No.04 - April (2011 vol.22)
pp: 544-557
Faizal Arya Samman , Techniche Universität Darmstadt, Fraunhofer Institut LBF, LOEWE-Zentrum AdRIA, Darmstadt and Hasanuddin University at Makassar, Indonesia
Thomas Hollstein , Tallin University of Technology, Estonia
Manfred Glesner , Techniche Universität Darmstadt, Darmstadt
A new theory for deadlock-free multicast routing especially used for on-chip interconnection network (NoC) is presented in this paper. The NoC router hardware solution that enables the deadlock-free multicast routing without utilizing virtual channels is introduced formally. The special characteristic of the NoC is that, wormhole packets can cut-through at flit-level and can be interleaved in the same channel with other flits of different packets by multiplexing it using a rotating flit-by-flit arbitration. The routing paths of each flit can be guaranteed correct because flits belonging to the same packet are labeled with the same local Id-tag on every communication channel. Hence, multicast deadlock problem can be solved at each router by further applying a hold-release tagging mechanism to control and manage conflicting multicast requests.
Network-on-chip, tree-based and multipath-based multicast routing, Id-tag-based wormhole packet switching, runtime adaptive routing and scheduling.
Faizal Arya Samman, Thomas Hollstein, Manfred Glesner, "New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip", IEEE Transactions on Parallel & Distributed Systems, vol.22, no. 4, pp. 544-557, April 2011, doi:10.1109/TPDS.2010.120
[1] G. Fox et al., "Fortran D Language Specification," Technical Report CRPC-TR 90079, Center for Research on Parallel Computation, Rice Univ., Dec. 1990.
[2] J. Merlin, "Techniques for the Automatic Parallelization of Distributed Fortran 90," Technical Report SNARC 92-02, Southampton Univ., Nov. 1991.
[3] High Performance Fortran Forum, "High Performance Fortran Language Specification, Version 1.0," Scientific Programming, vol. 2, no. 1, May/June 1993.
[4] Message Passing Interface Forum, "MPI-2: Extensions to the Message-Passing Interface," technical report, Univ. of Tennessee, Nov. 2003.
[5] G.A. Geist, J.A. Kohl, and P.M. Papadopoulos, "PVM and MPI: A Comparison of Features," Calculateurs Paralleles, vol. 8, no. 2, pp. 137-150, May 1996.
[6] G.A. Geist, A. Beguelin, J. Dongarra, W. Jiang, R. Manchek, and V. Sunderam, PVM: Parallel Virtual Machine: A User's Guide and Tutorial for Networked Parallel Computing, MIT Press, http://www.csm.ornl.govpvm, 1994.
[7] X. Lin, P.K. McKinley, and L.M. Ni, "Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers," IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 8, pp. 793-804, Aug. 1994.
[8] J. Duato, "A Theory of Deadlock-Free Adaptive Multicast Routing in Wormhole Networks," IEEE Trans. Parallel and Distributed Systems, vol. 6, no. 9, pp. 976-987, Sept. 1995.
[9] R.V. Boppana, S. Chalasani, and C.S. Raghavendra, "Resource Deadlocks and Performance of Wormhole Multicast Routing Algorithms," IEEE Trans. Parallel and Distributed Systems, vol. 9, no. 6, pp. 535-549, June 1998.
[10] M. Barnett, D.G. Payne, R.A. van de Geijn, and J. Watts, "Broadcasting on Meshes with Worm-Hole Routing," J. Parallel and Distributed Computing, vol. 35, no. 2, pp. 111-122, 1996.
[11] M.P. Malumbres, J. Duato, and J. Torrelas, "An Efficient Implementation of Tree-Based Multicast Routing for Distributed Shared-Memory Multiprocessors," Proc. Eighth IEEE Symp. Parallel and Distributed Processing, pp. 186-189, 1996.
[12] D.R. Kumar and W.A. Najjar, P.K. Srimani, "A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes," IEEE Trans. Computers, vol. 50, no. 7, pp. 647-659, July 2001.
[13] P. Abad, V. Puente, and J.-A. Gregorio, "MRR: Enabling Fully Adaptive Multicast Routing for CMP Interconnection Networks" Proc. 15th IEEE Int'l Symp. High Performance Computer Architecture (HPCA '09), pp. 355-366, Feb. 2009.
[14] S. Rodrigo, J. Flich, J. Duato, and M. Hummel, "Efficient Unicast and Multicast Support for CMPs," Proc. 41st IEEE/ACM Int'l Symp. Microarchitecture (MICRO '08), pp. 364-375, Nov. 2008.
[15] L. Wang, Y. Jin, H. Kim, and E.J. Kim, "Recursive Partitioning Multicast: A Bandwidth-Efficient Routing for Networks-on-Chip," Proc. Third ACM/IEEE Int'l Symp. Networks-on-Chip (NOCS '09), pp. 64-73, May 2009.
[16] N.E. Jerger, L.-S. Peh, and M. Lipasti, "Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support," Proc. 35th Int'l Symp. Computer Architecture (ISCA '08), pp. 229-240, June 2008.
[17] A.S. Vaidya, A. Sivasubramaniam, and C.R. Das, "Impact of Virtual Channels and Adaptive Routing on Application Performance," IEEE Trans. Parallel and Distributed Systems, vol. 12, no. 2, pp. 223-237, Feb. 2001.
[18] K. Aoyama and A.A. Chien, "The Cost of Adaptivity and Virtual Lanes in a Wormhole Router," J. VLSI Design, vol. 2, no. 4, pp. 315-333, 1995.
[19] D.A. Ilitzky, J.D. Hoffman, A. Chun, and B.P. Esparza, "Architecture of the Scalable Communications Core's Network on Chip," IEEE Micro, vol. 27, no. 5, pp. 62-74, Sep./Oct. 2007.
[20] P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, and D. Burger, "On-Chip Interconnection Networks of the TRIPS Chip," IEEE Micro, vol. 27, no. 5, pp. 41-50, Sep./Oct. 2007.
[21] C.J. Glass and L.M. Ni, "The Turn Model for Adaptive Routing," Proc. 19th Int'l Symp. Computer Architecture, pp. 278-287, 1992.
[22] W.J. Dally and C.L. Seitz, "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks," IEEE Trans. Computers, vol. C-36, no. 5, pp. 547-553, May 1987.
[23] J. Duato, "A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks," IEEE Trans. Parallel and Distributed Systems, vol. 4, no. 12, pp. 1320-1331, Dec. 1993.
[24] F.A. Samman, T. Hollstein, and M. Glesner, "Multicast Parallel Pipeline Router Architecture for Network-on-Chip," Proc. Design, Automation and Test in Europe Conf. and Exhibition (DATE '08), pp. 1396-1401, 2008.
[25] F.A. Samman, T. Hollstein, and M. Glesner, "Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip," IEEE Trans. Very Large Scale Integration Systems, vol. 18, no. 7, pp. 1067-1080, July 2010.
[26] F.A. Samman, T. Hollstein, and M. Glesner, "Planar Adaptive Router Microarchitecture for Tree-Based Multicast Network-on-Chip," Proc. First Int'l Workshop Network-on-Chip Architecture (NoCArch '08), in conj. with the IEEE/ACM Int'l Symp. Microarchitecture (MICRO-41), pp. 6-13, 2008.
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