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Issue No.02 - February (2011 vol.22)

pp: 296-308

Ivan Radojevic , New Zealand Defense Force, Auckland

Zoran Salcic , University of Auckland, Auckland

Partha S. Roop , University of Auckland, Auckland

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2010.69

ABSTRACT

The use of formal models of computation in dealing with increasing complexity of embedded systems design is gaining attention. A successful model of computation must be able to handle both control-dominated and data-dominated behaviors, which are most often simultaneously present in complex embedded systems. Besides behavioral heterogeneity, direct support for modeling distributed systems is also desirable, since an increasing number of embedded systems belong to this category. In this paper, we present distributed DFCharts (DDFCharts), a language based on a formal model that targets distributed heterogeneous embedded systems. Its top hierarchical level is made suitable to capture distributed systems. Behavioral heterogeneity is addressed by composing finite-state machines (FSMs) and synchronous dataflow graphs (SDFGs). We illustrate modeling in DDFCharts with practical examples and describe its implementation on heterogeneous target architecture.

INDEX TERMS

Formal languages, modeling, specification languages, heterogeneous systems.

CITATION

Ivan Radojevic, Zoran Salcic, Partha S. Roop, "Design of Distributed Heterogeneous Embedded Systems in DDFCharts",

*IEEE Transactions on Parallel & Distributed Systems*, vol.22, no. 2, pp. 296-308, February 2011, doi:10.1109/TPDS.2010.69REFERENCES

- [1] E.A. Lee and S. Neuendorffer, "Concurrent Models of Computation for Embedded Software,"
IEE Computers and Digital Techniques, vol. 152, no. 2, Mar. 2005.- [2] A. Jantsch and I. Sander, "Models of Computation and Languages for Embedded System Design,"
IEE Computers and Digital Techniques, vol. 152, no. 2, Mar. 2005.- [3] L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm,"
Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.- [4] G. Kahn, "The Semantics of a Simple Language for Parallel Programming,"
Proc. IFIP Congress 74, Aug. 1974.- [5] E.A. Lee and D.G. Messerschmitt, "Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing,"
IEEE Trans. Computers, vol. 36, no. 1, pp. 24-35, Jan. 1987.- [6] J.T. Buck, "Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model," Technical Report UCB/ERL 93/69, Dept. of EECS, Univ. of California Berkeley, 1993.
- [7] G. Bilsen, M. Engels, R. Lauwereins, and J.A. Peperstraete, "Cyclo-Static Dataflow,"
IEEE Trans. Signal Processing, vol. 44, no. 2, Feb. 1996.- [8] A. Benveniste and G. Berry, "The Synchronous Approach to Reactive and Real-Time Systems,"
Proc. IEEE, vol. 79, no. 9, pp. 1270-1282, Sept. 1991.- [9]
Esterel v7 Manual, www.esterel-technologies.com, 2010.- [10] F. Maraninchi and Y. Remond, "Argos: An Automaton-Based Synchronous Language,"
Computer Languages, vol. 27, nos. 1-3, pp. 61-92, Oct. 2001.- [11] N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud, "The Synchronous Data Flow Programming Language LUSTRE,"
Proc. IEEE, vol. 79, no. 9, pp. 1305-1320, Sept. 1991.- [12] P. Le Guernic, T. Gautier, M. Le Borgne, and C. Le Maire, "Programming Real-Time Applications with SIGNAL,"
Proc. IEEE, vol. 79, no. 9, pp. 1321-1336, Sept. 1991.- [13] J. Eker et al., "Taming Heterogeneity—the Ptolemy Approach,"
Proc. IEEE, vol. 91, no. 1, pp. 127-144, Jan. 2003.- [14] C. Hoare, "Communicating Sequential Processes,"
Comm. ACM, vol. 21, no. 8, pp. 666-677, Aug. 1978.- [15] R. Milner,
Communication and Concurrency. Prentice-Hall, 1989.- [16] I. Radojevic, Z. Salcic, and P. Roop, "Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation,"
Proc. Int'l Conf. VLSI Design, Jan. 2006.- [17] I. Radojevic, Z. Salcic, and P. Roop, "Modeling Embedded Systems: From SystemC and Esterel to DFCharts,"
IEEE Design and Test of Computers, vol. 23, no. 5, pp. 348-358, Sept. 2006.- [18] I. Radojevic, Z. Salcic, and P. Roop, "McCharts and Multiclock FSMs for Modelling Large Scale Systems,"
Proc. Fifth ACM-IEEE Int'l Conf. Formal Methods and Models for Codesign (MEMOCODE '07), May/June 2007.- [19] Z. Salcic and R. Mikhael, "A New Method for Instantaneous Power System Frequency Measurement Using Reference Points Detection,"
Electric Power Systems Research vol. 55, no. 2, pp. 97-102, Aug. 2000.- [20] F. Balarin et al.,
Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer Academic Publishers, 1997.- [21] Z. Salcic, D. Hui, P. Roop, and M. Biglari-Abhari, "REMIC— Design of a Reactive Embedded Microprocessor Core,"
Proc. Asia-South Pacific Design Automation Conf. (ASP-DAC '05), Jan. 2005.- [22] www.altera.com, 2010.
- [23] Z. Salcic, D. Hui, P. Roop, and M. Biglari-Abhari, "HiDRA—A Reactive Multiprocessor Architecture for Heterogeneous Embedded Systems,"
Microprocessors and Microsystems, vol. 30, no. 2, pp. 72-85, Mar. 2006.- [24] A. Kalavade and E.A. Lee, "A Hardware-Software Codesign Methodology for DSP Applications,"
IEEE Design and Test of Computers, vol. 10, no. 3, pp. 16-28, July-Sept. 1993.- [25] S. Ramesh, "Implementation of Communicating Reactive Processes,"
Parallel Computing, vol. 25, no. 6, pp. 703-727, 1999.- [26] A. Girault, B. Lee, and E.A. Lee, "Hierarchical Finite State Machines with Multiple Concurrency Models,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 742-760, June 1999.- [27]
SCADE Product Manual, www.esterel-technologies.com, 2010.- [28] A. Girault, "A Survey of Automatic Distribution Methods for Synchronous Programs,"
Proc. Workshop Synchronous Languages Applications and Programs (SLAP 05), Apr. 2005.- [29] G. Berry, S. Ramesh, and R.K. Shyamasundar, "Communicating Reactive Processes,"
Proc. ACM SIGPLAN-SIGACT Symp. Principles of Programming Languages, Jan. 1993.- [30] S. Ramesh, "Communicating Reactive State Machines: Design, Model and Implementation,"
Pric. IFAC Workshop Distributed Computer Control Systems, Sept. 1998.- [31] F. Gruian, P. Roop, Z. Salcic, and I. Radojevic, "The SystemJ Approach to System-Level Design,"
Proc. Formal Methods and Models for Co-Design (MEMOCODE '06), July 2006.- [32] G. Berry and E. Sentovich, "Multiclock Esterel,"
Proc. Conf. Correct Hardware Design and Verification Methods (CHARME), Sept. 2001. |