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Issue No.02 - February (2011 vol.22)
pp: 217-230
Michihiro Koibuchi , National Institute of Informatics (NII), Tokyo
Tomohiro Otsuka , Keio University, Yokohama
Tomohiro Kudoh , National Institute of Advanced Industrial Science and Technology, Tsukuba
Hideharu Amano , Keio University, Yokohama
Ethernet has been used for connecting hosts in PC clusters, besides its use in local area networks. Although a layer-2 Ethernet topology is limited to a tree structure because of the need to avoid broadcast storms and deadlocks of frames, various deadlock-free routing algorithms on topologies that include loops suitable for parallel processing can be employed by the application of IEEE 802.1Q VLAN technology. However, the MPI communication libraries used in current PC clusters do not always support tagged VLAN technology; therefore, at present, the design of VLAN-based Ethernet cannot be applied to such PC clusters. In this study, we propose a switch-tagged routing methodology in order to implement various deadlock-free routing algorithms on such PC clusters by using at most the same number of VLANs as the degree of a switch. Since the MPI communication libraries do not need to perform VLAN operations, the proposed methodology has advantages in both simple host configuration and high portability. In addition, when it is used with on/off and multispeed link regulation, the power consumption of Ethernet switches can be reduced. Evaluation results using NAS parallel benchmarks showed that the performance of the topologies that include loops using the proposed methodology was comparable to that of an ideal one-switch (full crossbar) network, and the torus topology in particular had up to a 27 percent performance improvement compared with a tree topology with link aggregation.
Ethernet, routing, deadlock avoidance, interconnection networks, PC clusters.
Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano, "A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet", IEEE Transactions on Parallel & Distributed Systems, vol.22, no. 2, pp. 217-230, February 2011, doi:10.1109/TPDS.2010.73
[1] PC Cluster Consortium, http:/, 2010.
[2] InfiniBand Trade Association, http:/, 2010.
[3] F. Petrini, W.C. Feng, A. Hoisie, S. Coll, and E. Frachtenberg, "The Quadrics Network (QsNet): High-Performance Clustering Technology," Proc. Hot Interconnets 9, pp. 125-130, Aug. 2001.
[4] M. Koibuchi, K. Watanabe, T. Otsuka, and H. Amano, "Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster," IEEE Trans. Parallel and Distributed Systems, vol. 16, no. 8, pp. 747-759, Aug. 2005.
[5] Top 500 Supercomputer Sites, http:/, 2010.
[6] T. Kudoh, H. Tezuka, M. Matsuda, Y. Kodama, O. Tatebe, and S. Sekiguchi, "VLAN-Based Routing: Multi-Path L2 Ethernet Network for HPC Clusters," Proc. IEEE Int'l Conf. Cluster Computing (Cluster), Sept. 2004.
[7] S. Sharma, K. Gopalan, S. Nanda, and T. Chiueh, "Viking: A Multi-Spanning-Tree Ethernet Architecture for Metropolitan Area and Cluster Networks," Proc. IEEE INFOCOM, pp. 2283-2294, Mar. 2004.
[8] T. Otsuka, M. Koibuchi, A. Jouraku, and H. Amano, "VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus," Proc. Int'l Conf. Parallel Processing (ICPP), pp. 567-576, June 2005.
[9] F.D. Pellegrini, D. Starobinski, M.G. Karpovsky, and L.B. Levitin, "Scalable Cycle-Breaking Algorithms for Gigabit Ethernet Backbones," Proc. IEEE INFOCOM, pp. 2175-2184, Mar. 2004.
[10] A. Jouraku, M. Koibuchi, and H. Amano, "An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks," IEEE Trans. Parallel and Distributed Systems, vol. 18, no. 3, pp. 320-333, Mar. 2007.
[11] A. Mejia, J. Flich, J. Duato, S.-A. Reinemo, and T. Skeie, "Boosting Ethernet Performance by Segment-Based Routing," Proc. 15th EUROMICRO Int'l Conf. Parallel, Distributed and Network-Based Processing, pp. 55-62, Feb. 2007.
[12] S.-A. Reinemo and T. Skeie, "Effective Shortest Path Routing for Gigabit Ethernet," Proc. IEEE Int'l Conf. Comm. (ICC), pp. 6419-6424, June 2007.
[13] R. Garcia, J. Duato, and J.J. Serrano, "A New Transparent Bridge Protocol for LAN Internetworking Using Topologies with Active Loops," Proc. Int'l Conf. Parallel Processing (ICPP), pp. 295-303, 1998.
[14] K. Lui, W. Lee, and K. Nahrstedt, "STAR: A Transparent Spanning Tree Bridge Protocol with Alternate Routing," ACM SIGCOMM Computer Comm. Rev., vol. 32, no. 3, pp. 33-46, July 2002.
[15] S. Urushidani, S. Abe, Y. Ji, K. Fukuda, M. Koibuchi, M. Nakamura, S. Yamada, K. Shimizu, R. Hayashi, I. Inoue, and K. Shiomoto, "Design of Versatile Academic Infrastructure for Multilayer Network Services," IEEE J. Selected Areas in Comm., vol. 27, no. 3, pp. 253-267, Apr. 2009.
[16] S. Miura, T. Boku, T. Okamoto, and T. Hanawa, "A Dynamic Routing Control System for High-Performance PC Cluster with Multi-Path Ethernet Connection," Proc. Workshop Comm. Architecture for Clusters (CAC) in IPDPS, pp. 1-8, Apr. 2008.
[17] W.D. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
[18] J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach. Morgan Kaufmann, 2002.
[19] V. Soteriou and L.-S. Peh, "Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks," IEEE Trans. Parallel and Distributed Systems, vol. 18, no. 3, pp. 393-408, Mar. 2007.
[20] IPTraf: IP Network Monitoring Software, http:/, 2010.
[21] T. Otsuka, M. Koibuchi, T. Kudoh, and H. Amano, "A Switch-Tagged VLAN Routing Methodology for PC Clusters with Ethernet," Proc. Int'l Conf. Parallel Processing (ICPP), pp. 479-486, Aug. 2006.
[22] C.J. Glass and L.M. Ni, "The Turn Model for Adaptive Routing," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 278-287, May 1992.
[23] GtrcNET-1, http://projects.gtrc.aist.go.jpgnet/, 2009.
[24] Tperf, /, 2010.
[25] O. Lysne, J.M. Montañana, J. Flich, J. Duato, T.M. Pinkston, and T. Skeie, "An Efficient and Deadlock-Free Network Reconfiguration Protocol," IEEE Trans. Computers, vol. 57, no. 6, pp. 762-779, June 2008.
[26] Intel MPI Benchmarks, asmo-na/eng219848.htm, 2010.
[27] The NAS Parallel Benchmarks, SoftwareNPB/, 2010.
[28] L. Shang, L.-S. Peh, and N.K. Jha, "Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks," Proc. Int'l Symp. High-Performance Computer Architecture, pp. 91-102, Jan. 2003.
[29] J.M. Stine and N.P. Carter, "Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction," IEEE Computer Architecture Letters, vol. 3, no. 1, pp. 14-17, Jan. 2004.
[30] M. Alonso, J.M. Martinez, V. Santonja, P. Lopez, and J. Duato, "Power Saving in Regular Interconnection Networks Built with High-Degree Switches," Proc. IEEE Int'l Parallel and Distributed Processing Symp. (IPDPS), Apr. 2005.
[31] M. Koibuch, T. Otsuka, H. Matsutani, and H. Amano, "An On/Off Link Activation Method for Low-Power Ethernet in PC Clusters," Proc. IEEE Int'l Symp. Parallel and Distributed Processing (IPDPS), May 2009.
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