Issue No. 12 - December (2010 vol. 21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2010.43
Alberto Ros , Universidad de Murcia, Murcia
Manuel E. Acacio , Universidad de Murcia, Murcia
José M. García , Universidad de Murcia, Murcia
Future many-core CMP designs that will integrate tens of processor cores on-chip will be constrained by area and power. Area constraints make impractical the use of a bus or a crossbar as the on-chip interconnection network, and tiled CMPs organized around a direct interconnection network will probably be the architecture of choice. Power constraints make impractical to rely on broadcasts (as, for example, Token-CMP does) or any other brute-force method for keeping cache coherence, and directory-based cache coherence protocols are currently being employed. Unfortunately, directory protocols introduce indirection to access directory information, which negatively impacts performance. In this work, we present DiCo-CMP, a novel cache coherence protocol especially suited to future many-core tiled CMP architectures. In DiCo-CMP, the task of storing up-to-date sharing information and ensuring ordered accesses for every memory block is assigned to the cache that must provide the block on a miss. Therefore, DiCo-CMP reduces the miss latency compared to a directory protocol by sending requests directly to the cache that provides the block in a cache miss. These latency reductions result in improvements in execution time of up to 6 percent, on average, over a directory protocol. In comparison with Token-CMP, our protocol only sends one request message for each cache miss, as such is able to reduce network traffic by 43 percent.
Many-core CMP, cache coherence protocol, direct coherence, indirection problem, on-chip network traffic.
A. Ros, J. M. García and M. E. Acacio, "A Direct Coherence Protocol for Many-Core Chip Multiprocessors," in IEEE Transactions on Parallel & Distributed Systems, vol. 21, no. , pp. 1779-1792, 2010.