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Issue No. 12 - December (2010 vol. 21)
ISSN: 1045-9219
pp: 1765-1778
José M. Cámara , University of Burgos, Burgos
Miquel Moretó , Universitat Politècnica de Catalunya, Barcelona
Enrique Vallejo , Universidad de Cantabria, Santander
Ramón Beivide , Universidad de Cantabria, Santander
José Miguel-Alonso , University of the Basque Country, San Sebastian
Carmen Martínez , Universidad de Cantabria, Santander
Javier Navaridas , University of the Basque Country, San Sebastian
Many current parallel computers are built around a torus interconnection network. Machines from Cray, HP, and IBM, among others, make use of this topology. In terms of topological advantages, square (2D) or cubic (3D) tori would be the topologies of choice. However, for different practical reasons, 2D and 3D tori with different number of nodes per dimension have been used. These mixed-radix topologies are not edge symmetric, which translates into poor performance due to an unbalanced use of network resources. In this work, we analyze twisted 2D and 3D mixed-radix tori that remove the network bottlenecks present in nontwisted ones. Such topologies recover edge symmetry, and consequently, balance the utilization of their links. The distance-related properties of twisted tori together with a full characterization of their bisection bandwidth are described in this paper. A simulation-based performance evaluation has been carried out to assess the network performance under synthetic and trace-driven workloads. The obtained results show noticeable and consistent performance gains (up to an increase of 74 percent in accepted load). In addition, we propose scalable and practicable packet routing mechanisms and wiring layouts for these interconnection systems. The complexity of the architectural proposals is similar to the one exhibited by routing and folding mechanisms in standard tori.
Multiprocessor interconnection, parallel architectures, routing, supercomputers.

C. Martínez et al., "Twisted Torus Topologies for Enhanced Interconnection Networks," in IEEE Transactions on Parallel & Distributed Systems, vol. 21, no. , pp. 1765-1778, 2010.
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