The Community for Technology Leaders
RSS Icon
Issue No.06 - June (2010 vol.21)
pp: 739-753
Teresa Nachiondo , Universidad Politécnica de Valencia, Valencia
Jose Flich , Universidad Politécnica de Valencia, Valencia
Jose Duato , Universidad Politécnica de Valencia, Valencia
Congestion management is likely to become a critical issue in interconnection networks, as increasing power consumption and cost concerns lead to improvements in the efficiency of network resources. In previous configurations, networks were usually oversized and underutilized. In a smaller network, however, contention is more likely to occur and blocked packets cause head-of-line (HoL) blocking among the rest of the packets, spreading congestion quickly. The best-known solution to HoL blocking is Virtual Output Queues (VOQs). However, the cost of implementing VOQs increases quadratically with the number of output ports in the network, making it unpractical. The situation is aggravated when several priorities and/or Quality of Service (QoS) levels must be supported. Therefore, a more scalable and cost-effective solution is required to reduce or eliminate HoL blocking. In this paper, we present a family of methodologies, referred to as Destination-Based Buffer Management (DBBM), to reduce/eliminate the HoL blocking effect on interconnection networks. DBBM efficiently uses the resources (mainly memory queues) of the network. These methodologies are comprehensively evaluated in terms of throughput, scalability, and fairness. Results show that using the DBBM strategy, with a reduced number of queues at each switch, it is possible to achieve roughly the same throughput as the VOQ mechanism. Moreover, all of the proposed strategies are designed in such a way that they can be used in any switch architecture. We compare DBBM with RECN, a sophisticated mechanism that eliminates HoL blocking in congestion situations. Our mechanism is able to achieve almost the same performance with very low logic requirements (in contrast with RECN).
Communication/networking and information technology, network architecture and design, network operating systems, distributed systems, computer systems organization.
Teresa Nachiondo, Jose Flich, Jose Duato, "Buffer Management Strategies to Reduce HoL Blocking", IEEE Transactions on Parallel & Distributed Systems, vol.21, no. 6, pp. 739-753, June 2010, doi:10.1109/TPDS.2009.63
[1] J.M. Anderson, S.P. Amarasinghe, and M.S. Lam, "Data and Computation Transformations for Multiprocessors," Proc. Fifth ACM SIGPLAN Symp. Principles and Practice of Parallel Programming (PPoPP), 1995.
[2] T. Anderson, S. Owicki, J. Saxe, and C. Thacker, "High Speed Switch Scheduling for Local Area Networks," ACM Trans. Computer Systems, vol. 11, pp. 319-352, Nov. 1993.
[3] L.S. Brakmo and L.L. Peterson, "TCP Vegas: End to End Congestion Avoidance on a Global Internet," IEEE J. Selected Areas in Comm., vol. 13, no. 8, pp. 1465-1480, Oct. 1995.
[4] J. Duato, J. Flich, and T. Nachiondo, "Cost-Effective Technique to Reduce HoL Blocking in Single-Stage and Multistage Switch Fabrics," Proc. Euromicro Conf. Parallel, Distributed and Network-Based, pp. 48-53, Feb. 2004.
[5] J. Duato, I. Johnson, J. Flich, F. Naven, P. García, and T. Nachiondo, "A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks," Proc. Int'l Symp. High-Performance Computer Architecture, Feb. 2005.
[6] P.J. Garca, J. Flich, J. Duao, I. Johnson, F.J. Quiles, and F. Naven, "Efficient, Scalable Congestion Management for Interconnection Networks," IEEE Micro, vol. 26, no. 5, pp. 52-66, Sept./Oct. 2006.
[7] W.J. Dally, "Virtual-Channel Flow Control," Proc. 17th Int'l Symp. Computer Architecture, pp. 60-68, May 1990.
[8] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004.
[9] W. Heirman, J. Dambre, J. Van Campenhout, C. Debaes, and H. Thienpont, "Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems," Proc. Reconfigurable Architectures Workshop, Apr. 2005.
[10] R. Jain, "A Delay-Based Approach for Congestion Avoidance in Interconnected Heterogeneous Computer Networks," ACM Computer Comm. Rev., vol. 19, no. 5, pp. 56-71, Oct. 1989.
[11] N.P. Jouppi, "Cache Write Policies and Performance," Proc. 20th Int'l Symp. Computer Architecture, 1991.
[12] T. Kudoh, S. Nishimura, J. Yamamoto, H. Nishi, O. Tatebe, and H. Amano, "RHiNET: A Network for High Performance Parallel Computing Using Locally Distributed Computing," Proc. Int'l Workshop Innovative Architectures (IWIA '99), pp. 69-73, Nov. 1999.
[13] N. McKeown, "Scheduling Algorithms for Input-Queued Cell Switches," PhD thesis, Univ. of California at Berkeley, 1995.
[14] T. Nachiondo, J. Flich, and J. Duato, "Efficient Reduction of HoL Blocking in Multistage Networks," Proc. Workshop Comm. Architecture for Clusters (CAC '05), Apr. 2005.
[15] T. Nachiondo, J. Flich, J. Duato, and M. Gusat, "Cost/Performance Trade Offs and Fairness Evaluation of Queue Mapping Policies," Proc. Int'l Euro-Par Conf., pp. 1025-1035, Aug. 2005.
[16] T. Nachiondo, J. Flich, and J. Duato, "Destination-Based HoL Blocking Elimination," Proc. 12th Int'l Conf. Parallel and Distributed Systems (ICPADS), July 2006.
[17] T. Nachiondo, "Buffer Management Strategies to Reduce HoL Blocking," PhD thesis, July 2006.
[18] S. Nishimura, T. Kudoh, H. Nishi, J. Yamamoto, K. Harasawa, N. Matsudaira, S. Akutsu, K. Tasho, and H. Amano, "Highspeed Network Switch RHiNET2/SW and Its Implementation with Optical Interconnections," Proc. Eighth Hot Interconnect, pp. 31-38, Aug. 2000.
[19] NPB Homepage,, 2009.
[20] Passive Measurement and Analysis Project's Homepage, http://pma.nlanr.netPMA, 2009.
[21] S.L. Scott and G. Thorson, "The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus," Proc. Hot Interconnects IV, Aug. 1996.
[22] J.P. Singh et al., "SPLASH: Stanford Parallel Applications for Shared-Memory Multiprocessors and Uniprocessors," Computer Architecture News, vol. 20, no. 1, pp. 5-44, May 1992.
[23] SSP Homepage, ssp/, 2007.
[24] J.M. Stine, N.P. Carter, and J. Flich, "Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction," IEEE Computer Architecture Letters, vol. 3, no. 1, p. 4, Jan. 2004.
[25] C. Ruemmler and J. Wilkes, "Unix Disk Access Patterns," Proc. Winter Usenix Conf., Jan. 1993.
[26] K. Watanabe et al., "Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster," IEEE Trans. Parallel and Distributed Systems, vol. 16, no. 8, pp. 747-759, Aug. 2005.
[27] S.C. Woo et al., "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. 22nd Int'l Symp. Computer Architecture, pp. 24-36, June 1995.
[28] IBM BG/L Team, "An Overview of BlueGene/L Supercomputer," Proc. ACM Supercomputing Conf., 2002.
[29] InfiniBand Trade Association, InfiniBand Architecture, Specification Volume 1, Release 1.0, http:/, 2009.
[30] Myrinet, 2000 Series Networking, multicomputer/products/ 2000_series_networking2000_ networking.htm , 2007.
[31] Quadrics QsNet, http:/, 2009.
[32] L. Shang, L.S. Peh, and N.K. Jha, "Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks," Proc. Int'l Symp. High-Performance Computer Architecture, pp. 91-102, Feb. 2003.
15 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool