Issue No.01 - January (2010 vol.21)
David A. Zier , NVIDIA Corporation, Beaverton
Ben Lee , Oregon State University, Corvallis
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2009.47
Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscalar processors. One promising method of exploiting TLP is Dynamic Speculative Multithreading (D-SpMT), which extracts multiple threads from a sequential program without compiler support or instruction set extensions. This paper introduces Cascadia, a D-SpMT multicore architecture that provides multigrain thread-level support and is used to evaluate the performance of several benchmarks. Cascadia applies a unique sustainable IPC (sIPC) metric on a comprehensive loop tree to select the best performing nested loop level to multithread. This paper also discusses the relationships that loops have on one another, in particular, how loop nesting levels can be extended through procedures. In addition, a detailed study is provided on the effects that thread granularity and interthread dependencies have on the entire system.
Multithreading processors, multicore processors, simulation, speculative multithreading.
David A. Zier, Ben Lee, "Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture", IEEE Transactions on Parallel & Distributed Systems, vol.21, no. 1, pp. 47-59, January 2010, doi:10.1109/TPDS.2009.47