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Issue No. 08 - August (2009 vol. 20)
ISSN: 1045-9219
pp: 1126-1141
D. Frank Hsu , Fordham University, New York
Yutaka Yamada , Keio University, Yokohama and Toshiba Corporation, Kawasaki
Michihiro Koibuchi , National Institute of Informatics, Tokyo
Hideharu Amano , Keio University, Yokohama
Hiroki Matsutani , Keio University, Yokohama
The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for low-latency and high-throughput communications using a modest silicon budget. In this paper, we propose a novel tree-based interconnection network called Fat H-Tree that meets these requirements. A Fat H-Tree provides a torus structure by combining two folded H-Tree networks and is an attractive alternative to tree-based networks such as the Fat Trees in a microarchitecture domain. We introduce its chip layout schemes based on a folding technique for 2D and 3D ICs. Three deadlock-free routing schemes are proposed for Fat H-Tree. We evaluate the performance of Fat H-Tree and other tree-based networks using real application traces. In addition, the network logic area, wire resource, and energy consumption of Fat H-Tree are compared with other topologies, based on a typical implementation of on-chip routers synthesized with a 90-nm standard cell library. The results show that 1) a Fat H-Tree outperforms a Fat Tree with two upward and four downward connections in terms of the throughput and average hop count, 2) a Fat H-Tree requires 19.8 percent-27.8 percent smaller network logic area than the Fat Tree, 3) a Fat H-Tree consumes slightly less energy than the Fat Tree does, and 4) a Fat H-Tree uses slightly more wire resources than the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat-H-Tree-based on-chip networks.
Interconnection networks, on-chip networks, network topology, tree, routing algorithm.
D. Frank Hsu, Yutaka Yamada, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani, "Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network", IEEE Transactions on Parallel & Distributed Systems, vol. 20, no. , pp. 1126-1141, August 2009, doi:10.1109/TPDS.2008.233
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