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Issue No.09 - September (2008 vol.19)
pp: 1201-1214
One of the critical goals in code optimization for Multi-Processor-System-on-a-Chip (MPSoC) architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely costly from both performance and power angles. While conventional data locality optimization techniques can be used for improving data access pattern of each processor independently, such techniques usually do not consider locality for shared data. This paper proposes a strategy that reduces the number of off-chip references due to shared data. It achieves this goal by restructuring a parallelized application code in such a fashion that a given data block is accessed by parallel processors within the same time frame, so that its reuse is maximized while it is in the on-chip memory space. This tends to minimize the number of off-chip references since the accesses to a given data block are clustered within a short period of time during execution. Our approach employs a polyhedral tool that helps us isolate computations that manipulate a given data block. In order to test the effectiveness of our approach, we implemented it using a publicly-available compiler infrastructure and conducted experiments with twelve data-intensive embedded applications. Our results show that optimizing data locality for shared data elements is very useful in practice.
Memory management, Compilers, Optimization, Multiprocessor Systems
Guilin Chen, Mahmut Kandemir, "Compiler-Directed Code Restructuring for Improving Performance of MPSoCs", IEEE Transactions on Parallel & Distributed Systems, vol.19, no. 9, pp. 1201-1214, September 2008, doi:10.1109/TPDS.2007.70760
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