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Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range in size from hundreds to several thousand dynamic instructions and have minimal dependences between them. However, recent work has shown that TLS can offer compelling performance improvements when targeting much larger speculative threads of more than 50,000 dynamic instructions per thread, with many frequent data dependences between them. To support such large and dependent speculative threads, hardware must be able to buffer the additional speculative state, and must also address the more challenging problem of tolerating the resulting cross-thread data dependences. In this article we present chipmultiprocessor (CMP) support for large speculative threads that integrates several previous proposals for TLS hardware. We also present support for sub-threads: a mechanism for tolerating crossthread data dependences by checkpointing speculative execution. Through an evaluation that exploits the proposed hardware support in the database domain, we find that the transaction response time for three of the five transactions from TPC-C (on a simulated 4-processor chip-multiprocessor) speed up by a factor of 1.9 to 2.9.
Multiprocessor Systems, thread-level speculation, databases, cache coherence

A. Ailamaki, G. Steffan, T. C. Mowry and C. B. Colohan, "CMP Support for Large and Dependent Speculative Threads," in IEEE Transactions on Parallel & Distributed Systems, vol. 18, no. , pp. 1041-1054, 2007.
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