Issue No. 06 - June (2007 vol. 18)
Mark E. Femal , IEEE
<p><b>Abstract</b>—Although users of high-performance computing are most interested in raw performance, both energy and power consumption have become critical concerns. One approach to lowering energy and power is to use high-performance cluster nodes that have several power-performance states so that the energy-time trade-off can be dynamically adjusted. This paper analyzes the energy-time trade-off of a wide range of applications—serial and parallel—on a power-scalable cluster. We use a cluster of frequency and voltage-scalable AMD-64 nodes, each equipped with a power meter. We study the effects of memory and communication bottlenecks via direct measurement of time and energy. We also investigate metrics that can, at runtime, predict when each type of bottleneck occurs. Our results show that, for programs that have a memory or communication bottleneck, a power-scalable cluster can save significant energy with only a small time penalty. Furthermore, we find that, for some programs, it is possible to <it>both</it> consume less energy <it>and</it> execute in less time by increasing the number of nodes while reducing the frequency-voltage setting of each node.</p>
High-performance computing, power-aware computing.
Mark E. Femal, David K. Lowenthal, Feng Pan, Rob Springer, Nandini Kappiah, Barry L. Rountree, Vincent W. Freeh, "Analyzing the Energy-Time Trade-Off in High-Performance Computing Applications", IEEE Transactions on Parallel & Distributed Systems, vol. 18, no. , pp. 835-848, June 2007, doi:10.1109/TPDS.2007.1026