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Issue No. 01 - January (2007 vol. 18)
ISSN: 1045-9219
pp: 84-95
Mei Yang , IEEE
<p><b>Abstract</b>—As a basic building block of a switch scheduler, a fast and fair arbiter is critical to the efficiency of the scheduler, which is the key to the performance of a high-speed switch or router. In this paper, we propose a parallel round-robin arbiter (PRRA) based on a simple binary search algorithm, which is specially designed for hardware implementation. We prove that our PRRA achieves round-robin fairness under all input patterns. We further propose an improved (IPRRA) design that reduces the timing of PRRA significantly. Simulation results with TSMC .18<tmath>\mu m</tmath> standard cell library show that PRRA and IPRRA can meet the timing requirement of a terabit <tmath>256\times256</tmath> switch. Both PRRA and IPRRA are much faster and simpler than the programmable priority encoder (PPE), a well-known round-robin arbiter design. We also introduce an additional design which combines PRRA and IPRRA and provides trade-offs in gate delay, wire delay, and circuit area. With the binary tree structure and high performance, our designs are scalable for large <tmath>N</tmath> and useful for implementing schedulers for high-speed switches and routers.</p>
Arbitration, circuits and systems, matching, parallel processing, round-robin arbiter, switch scheduling.

M. Yang and S. Q. Zheng, "Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters," in IEEE Transactions on Parallel & Distributed Systems, vol. 18, no. , pp. 84-95, 2007.
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