The Community for Technology Leaders
Green Image
<p><b>Abstract</b>—To support a global virtual memory space, an architecture must translate virtual addresses dynamically. In current processors, the translation is done in a TLB (Translation Lookaside Buffer), before or in parallel with the first-level cache access. As processor technology improves at a rapid pace and the working sets of new applications grow insatiably, the latency and bandwidth demands on the TLB are difficult to meet, especially in multiprocessor systems, which run larger applications and are plagued by the TLB consistency problem. We describe and compare five options for virtual address translation in the context of Distributed Shared Memory (DSM) multiprocessors, including CC-NUMAs (Cache-Coherent Non-Uniform Memory Access Architectures) and COMAs (Cache Only Memory Access Architectures). In CC-NUMAs, moving the TLB to shared memory is a bad idea because page placement, migration, and replication are all constrained by the virtual page address, which greatly affects processor node access locality. In the context of COMAs, the allocation of pages to processor nodes is not as critical because memory blocks can dynamically migrate and replicate freely among nodes. As the address translation is done deeper in the memory hierarchy, the frequency of translations drops because of the filtering effect. We also observe that the TLB is very effective when it is merged with the shared-memory, because of the sharing and prefetching effects and because there is no need to maintain TLB consistency. Even if the effectiveness of the TLB merged with the shared memory is very high, we also show that the TLB can be removed in a system with address translation done in memory because the frequency of translations is very low.</p>
Multiprocessors, distributed shared memory, virtual memory, simulations, dynamic address translation, virtual-address caches.

M. Dubois and X. Qiu, "Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors," in IEEE Transactions on Parallel & Distributed Systems, vol. 16, no. , pp. 612-623, 2005.
82 ms
(Ver 3.3 (11022016))