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<p><b>Abstract</b>—The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of Network-on-Chip (<it>NoC</it>) architectures that have been proposed recently for System-on-Chip (<it>SoC</it>) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This paper illustrates a complete synthesis flow, called <tt>NetChip</tt>, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (<tt>SUNMAP</tt>, <tmath>\times</tmath><tt>pipesCompiler</tt>). The entire flow leverages the flexibility of a fully reusable and scalable network components library called <tmath>\times</tmath><tt>pipes</tt>, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented in the paper, showing the powerful design space exploration capabilities of the proposed methodology and tools.</p>
Systems-on-chip, networks on chip, synthesis, mapping, architecture.
Davide Bertozzi, Luca Benini, Stergios Stergiou, Antoine Jalabert, Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli, "NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip", IEEE Transactions on Parallel & Distributed Systems, vol. 16, no. , pp. 113-129, February 2005, doi:10.1109/TPDS.2005.22
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