Issue No. 05 - May (2000 vol. 11)

ISSN: 1045-9219

pp: 459-474

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.852399

ABSTRACT

<p><b>Abstract</b>—This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the <it>parity strategy</it> which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of <it>N</it>/2<b></b> comparators plus an <tmath>$\Omega$</tmath>-network of <tmath>$(\log N- 1)$</tmath> switch levels. This network reduces the cost complexity to <tmath>$O(N \log N)$</tmath> compared with the <tmath>$O(N \log^{2} N)$</tmath> of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so <it>N</it>/2 keys are wired straight through the network.</p>

INDEX TERMS

Bitonic sorting, parallel computing, sorting networks, omega networks, sorting, minimizing communication.

CITATION

Kenneth E. Batcher, Jae-Dong Lee, "Minimizing Communication in the Bitonic Sort",

*IEEE Transactions on Parallel & Distributed Systems*, vol. 11, no. , pp. 459-474, May 2000, doi:10.1109/71.852399