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<p><b>Abstract</b>—We present efficient parallel matrix multiplication algorithms for linear arrays with reconfigurable pipelined bus systems (LARPBS). Such systems are able to support a large volume of parallel communication of various patterns in constant time. An LARPBS can also be reconfigured into many independent subsystems and, thus, is able to support parallel implementations of divide-and-conquer computations like Strassen's algorithm. The main contributions of the paper are as follows: We develop five matrix multiplication algorithms with varying degrees of parallelism on the LARPBS computing model, namely, MM<sub>1</sub>, MM<sub>2</sub>, MM<sub>3</sub>, and compound algorithms <tmath>${\cal C}_1(\epsilon)$</tmath> and <tmath>${\cal C}_2(\delta).$</tmath> Algorithm <tmath>${\cal C}_1(\epsilon)$</tmath> has adjustable time complexity in sublinear level. Algorithm <tmath>${\cal C}_2(\delta)$</tmath> implies that it is feasible to achieve sublogarithmic time using <it>o</it>(<it>N</it><super>3</super>) processors for matrix multiplication on a realistic system. Algorithms MM<sub>3</sub>, <tmath>${\cal C}_1(\epsilon),$</tmath> and <tmath>${\cal C}_2(\delta)$</tmath> all have <it>o</it>(<it>N</it><super>3</super>) cost and, hence, are very processor efficient. Algorithms MM<sub>1</sub>, MM<sub>3</sub>, and <tmath>${\cal C}_1(\epsilon)$</tmath> are general-purpose matrix multiplication algorithms, where the array elements are in any ring. Algorithms MM<sub>2</sub> and <tmath>${\cal C}_2(\delta)$</tmath> are applicable to array elements that are integers of bounded magnitude, or floating-point values of bounded precision and magnitude, or Boolean values. Extension of algorithms MM<sub>2</sub> and <tmath>${\cal C}_2(\delta)$</tmath> to unbounded integers and reals are also discussed.</p>
Compound algorithm, linear array, matrix multiplication, optical pipelined bus, reconfigurability, Strassen's algorithm.

S. Q. Zheng, K. Li and Y. Pan, "Fast and Processor Efficient Parallel Matrix Multiplication Algorithms on a Linear Array With a Reconfigurable Pipelined Bus System," in IEEE Transactions on Parallel & Distributed Systems, vol. 9, no. , pp. 705-720, 1998.
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