Issue No. 02 - February (1998 vol. 9)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.663870
<p><b>Abstract</b>—Many significant engineering and scientific problems involve optimization of some criteria over a combinatorial configuration space. The two methods most often used to solve these problems effectively—simulated annealing (SA) and genetic algorithms (GA)—do not easily lend themselves to massive parallel implementations. Simulated annealing is a naturally serial algorithm, while GA involves a selection process that requires global coordination. This paper introduces a new hybrid algorithm that inherits those aspects of GA that lend themselves to parallelization, and avoids serial bottle-necks of GA approaches by incorporating elements of SA to provide a completely parallel, easily scalable hybrid GA/SA method. This new method, called Genetic Simulated Annealing, does not require parallelization of any problem specific portions of a serial implementation—existing serial implementations can be incorporated as is. Results of a study on two difficult combinatorial optimization problems, a 100 city traveling salesperson problem and a 24 word, 12 bit error correcting code design problem, performed on a 16K PE MasPar MP-1, indicate advantages over previous parallel GA and SA approaches. One of the key results is that the performance of the algorithm scales up linearly with the increase of processing elements, a feature not demonstrated by any previous parallel GA or SA approaches, which enables the new algorithm to utilize massive parallel architecture with maximum effectiveness. Additionally, the algorithm does not require careful choice of control parameters, a significant advantage over SA and GA.</p>
Genetic algorithms, simulated annealing, parallel algorithms, SIMD, combinatorial optimization, hybrid methods, traveling salesperson, massive parallelism, error correcting codes.
N. S. Flann, D. W. Watson and H. Chen, "Parallel Genetic Simulated Annealing: A Massively Parallel SIMD Algorithm," in IEEE Transactions on Parallel & Distributed Systems, vol. 9, no. , pp. 126-136, 1998.