Issue No. 09 - September (1997 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.615440
<p><b>Abstract</b>—For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent years. As a result, several shared-memory multiprocessors consist of more memory banks than processors. The object of this paper is to provide a simple model (with only a few parameters) for the design and analysis of irregular parallel algorithms that will give a reasonable characterization of performance on such machines. For this purpose, we extend Valiant's bulk-synchronous parallel (<scp>BSP</scp>) model with two parameters: a parameter for memory bank <it>delay</it>, the minimum time for servicing requests at a bank, and a parameter for memory bank <it>expansion</it>, the ratio of the number of banks to the number of processors. We call this model the (<it>d</it>, <b>x</b>)-<scp>BSP</scp>. We show experimentally that the (<it>d</it>, <b>x</b>)-<scp>BSP</scp> captures the impact of bank contention and delay on the <scp>CRAY</scp> C90 and J90 for irregular access patterns, without modeling machine-specific details of these machines. The model has clarified the performance characteristics of several unstructured algorithms on the <scp>CRAY</scp> C90 and J90, and allowed us to explore tradeoffs and optimizations for these algorithms. In addition to modeling individual algorithms directly, we also consider the use of the (<it>d</it>, <b>x</b>)-<scp>BSP</scp> as a bridging model for emulating a very high-level abstract model, the Parallel Random Access Machine (<scp>PRAM</scp>). We provide matching upper and lower bounds for emulating the <scp>EREW</scp> and <scp>QRQW PRAM</scp>s on the (<it>d</it>, <b>x</b>)-<scp>BSP</scp>.</p>
Memory bank contention, memory delays, parallel machine models, performance analysis, parallel algorithms, shared memory, multiprocessors.
Marco Zagha, Phillip B. Gibbons, Yossi Matias, Guy E. Blelloch, "Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors", IEEE Transactions on Parallel & Distributed Systems, vol. 8, no. , pp. 943-958, September 1997, doi:10.1109/71.615440