Issue No. 05 - May (1997 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.598278
<p><b>Abstract</b>—An <it>O</it>(1) time algorithm to multiply two <it>N</it>-bit binary numbers using an <it>N</it>×<it>N</it> bit-model of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader Transform. The algorithm is extended to result in <it>AT</it><super>2</super> optimality over <tmath>$1\le T\le \sqrt N$</tmath> in a variant of the bit-model of VLSI.</p>
Integer multiplication, reconfigurable mesh, optimal algorithm, area-time trade off, VLSI architecture.
J. Jang, V. K. Prasanna and H. Park, "An Optimal Multiplication Algorithm on Reconfigurable Mesh," in IEEE Transactions on Parallel & Distributed Systems, vol. 8, no. , pp. 521-532, 1997.