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<p><b>Abstract</b>—The serialization of memory accesses is a major limiting factor in high performance SIMD computers. The data patterns or <it>templates</it> that are accessed by a program can be perceived by the compiler, and, therefore, the design of dynamic storage schemes that minimize conflicts may dramatically improve performance.</p><p>The problem of finding storage schemes that minimize the access time of arbitrary sets of power-of-two data patterns is proved to be NP-complete. We propose linear address transformations that can be dynamically applied by each processing element for mapping array references onto memories. An efficient approach for <it>combining</it> the constraints of different access patterns into <it>one single linear address transformation</it> is presented. We prove that finding the transformation that minimizes the access time is reducible to N-coloring, where N is the number of parallel memories. Using coloring heuristics, storage schemes are investigated with respect to minimizing the implementation cost (perfect storage) and overall access conflicts (semiperfect storage).</p><p>Results show that the perfect-storage may deviate on the average by 20% from the optimum access time in the case of 10 arbitrary data patterns and 16 memories. However, semiperfect schemes lead to dramatic reduction of the degree of conflict compared to perfect-schemes. The proposed heuristic storage largely outperforms interleaving and row-column-diagonals storages. The method can be implemented as compiler procedure for synthesizing storage schemes that promote parallel access to arbitrary sets of data patterns.</p>
Boolean matrices, heuristics, memory organization, NP-complete, parallel memories, performance evaluation, storage schemes.

M. A. Al-Mouhamed and S. S. Seiden, "A Heuristic Storage for Minimizing Access Time of Arbitrary Data Patterns," in IEEE Transactions on Parallel & Distributed Systems, vol. 8, no. , pp. 441-447, 1997.
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