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<p><b>Abstract</b>—The rapid advances in high-performance computer architecture and compilation techniques provide both challenges and opportunities to exploit the rich solution space of software pipelined loop schedules. In this paper, we develop a framework to construct a software pipelined loop schedule which runs on the given architecture (with a fixed number of processor resources) at the maximum possible iteration rate (á la rate-optimal) while minimizing the number of buffers—a close approximation to minimizing the number of registers.</p><p>The main contributions of this paper are: First, we demonstrate that such problem can be described by a simple mathematical formulation with precise optimization objectives under a periodic linear scheduling framework. The mathematical formulation provides a clear picture which permits one to visualize the overall solution space (for rate-optimal schedules) under different sets of constraints. Secondly, we show that a precise mathematical formulation and its solution does make a significant performance difference. We evaluated the performance of our method against three leading contemporary heuristic methods. Experimental results show that the method described in this paper performed significantly better than these methods.</p><p>The techniques proposed in this paper are useful in two different ways: 1) As a compiler option which can be used in generating faster schedules for performance-critical loops (if the interested users are willing to trade the cost of longer compile time with faster runtime). 2) As a framework for compiler writers to evaluate and improve other heuristics-based approaches by providing quantitative information as to where and how much their heuristic methods could be further improved.</p>
Instruction-level parallelism, instruction scheduling, integer linear programming, software pipelining, superscalar and VLIW architectures.

E. R. Altman, G. R. Gao and R. Govindarajan, "A Framework for Resource-Constrained Rate-Optimal Software Pipelining," in IEEE Transactions on Parallel & Distributed Systems, vol. 7, no. , pp. 1133-1149, 1996.
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