Issue No. 08 - August (1996 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.532116
<p><b>Abstract</b>—In this paper, a memory system is introduced for the efficient construction of a Gaussian pyramid. The memory system consists of an address calculating circuit, an address routing circuit, a memory module selection circuit, and <tmath>$2^n+1$</tmath> memory modules. The memory system provides parallel access to <tmath>$2^n$</tmath> image points whose patterns are a block, a row or a column, where the interval of the column and the block is 1 and the interval of the row is <tmath>$2^l,l\ge 0.$</tmath>.</p><p>The performance of a generic SIMD(Single-Instruction Multiple-Data) processor using the proposed memory system is compared with one using an interleaved memory system for the construction of a Gaussian pyramid. The ratio of the time of the construction of level 2 and level 10 from the original image (level 0) of an SIMD processor with an interleaved memory system to that of the proposed memory system is 1.485 and 1.633, respectively.</p>
SIMD memory architecture, parallel memory systems, address calculating circuit, data routing circuit, Gaussian pyramid algorithms, image processing.
J. W. Park and D. T. Harper, III, "An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid," in IEEE Transactions on Parallel & Distributed Systems, vol. 7, no. , pp. 855-860, 1996.