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<p><b>Abstract</b>—A methodology, called <it>Subsystem Access Time</it> (SAT) modeling, is proposed for the performance modeling and analysis of shared-bus multiprocessors. The methodology is <it>subsystem-oriented</it> because it is based on a <it>Subsystem Access Time Per Instruction</it> (SATPI) concept, in which we treat major components other than processors (e.g., off-chip cache, bus, memory, I/O) as <it>subsystems</it> and model for each of them the mean access time per instruction from each processor.</p><p>The SAT modeling methodology is derived from the <it>Customized Mean Value Analysis</it> (CMVA) technique, which is <it>request-oriented</it> in the sense that it models the weighted total mean delay for each type of request processed in the subsystems. The subsystem-oriented view of the proposed methodology facilitates divide-and-conquer modeling and bottleneck analysis, which is rarely addressed previously. These distinguishing features lead to a simple, general, and systematic approach to the analytical modeling and analysis of complex multiprocessor systems.</p><p>To illustrate the key ideas and features that are different from CMVA, an example performance model of a particular shared-bus multiprocessor architecture is presented. The model is used to conduct performance evaluation for throughput prediction. Thereby, the SATPIs of the subsystems are directly utilized to identify the bottleneck subsystem and find the requests or subsystem components that cause the bottleneck. Furthermore, the SATPIs of the subsystems are employed to explore the impact of several performance influencing factors, including memory latency, number of processors, data bus width, as well as DMA transfer.</p>
Bottleneck analysis, DMA transfer, performance analysis, separated address bus and data bus, shared-bus multiprocessor system, subsystem access time modeling, subsystem interferences.
Tai-Ming Parng, Chiung-San Lee, "A Subsystem-Oriented Performance Analysis Methodology for Shared-Bus Multiprocessors", IEEE Transactions on Parallel & Distributed Systems, vol. 7, no. , pp. 755-767, July 1996, doi:10.1109/71.508254
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