Issue No. 09 - September (1995 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.466631
<p><it>Abstract</it>—We propose a simple solution to the problem of efficient stack evaluation of LRU multiprocessor cache memories with arbitrary set-associative mapping. It is an extension of the existing stack evaluation techniques for all set-associative LRU uniprocessor caches. Special marker entries are used in the stack to represent data blocks (or lines) deleted by an invalidation-based cache coherence protocol. A method of marker-splitting is employed when a data block below a marker in the stack is accessed. Using this technique, one-pass trace evaluation of memory access trace yields hit ratios for all cache sizes and set-associative mappings of multiprocessor caches in a single pass over a memory reference trace. Simulation experiments on some multiprocessor trace data show an order-of-magnitude speed-up in simulation time using this one-pass technique.</p>
Cache memory, coherence by invalidation, set-associative, simulation, stack evaluation.
Y. Wu and R. Muntz, "Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches," in IEEE Transactions on Parallel & Distributed Systems, vol. 6, no. , pp. 930-942, 1995.