Issue No. 09 - September (1995 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.466630
<p><it>Abstract</it>—We describe a simulator which emulates the activity of a shared memory, common bus multiprocessor system with private caches. Both kernel and user program activities are considered, thus allowing an accurate analysis and evaluation of coherence protocol performance. The simulator can generate synthetic traces, based on a wide set of input parameters which specify processor, kernel and workload features. Other parameters allow us to detail the multiprocessor architecture for which the analysis has to be carried out. An actual-trace-driven simulation is possible, too, in order to evaluate the performance of a specific multiprocessor with respect to a given workload, if traces concerning this workload are available. In a separate section, we describe how actual traces can also be used to extract a set of input parameters for synthetic trace generation. Finally, we show how the simulator may be successfully employed to carry out a detailed performance analysis of a specific coherence protocol.</p>
Cache memory, multiple cache consistency, coherence protocol, multiprocessor, performance analysis, trace-driven simulation.
G. Prina, L. Ricciardi and C. A. Prete, "A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems," in IEEE Transactions on Parallel & Distributed Systems, vol. 6, no. , pp. 915-929, 1995.