Issue No. 08 - August (1995 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.406961
<p><it>Abstract</it>—VLIW processors use multiway branch instructions to achieve high-speed, parallel evaluation of control structures. This paper introduces a new multiway branch mechanism that allows constant-time branch-target resolution based on an arbitrary condition tree. The unique feature of this mechanism is its target selection unit, which yields a branch-target based on a set of condition bit values and a condition tree description. A representation of condition trees that results in a compact target selection unit is described, and the logic diagram of a target selection unit that provides a four-way branching is shown. Our experimental results on nontrivial integer benchmarks indicate that the proposed multiway branch unit can improve the performance of VLIW machines substantially (i.e., as much as a geometric mean of 35%), compared to using the conventional two-way branching.</p>
Instruction-level parallelism, generalized multiway branching, VLIW microprocessor, condition tree, mirror normalization, VLIW compiler, superscalar microprocessor.
Soo-Mook Moon, Scott D. Carson, "Generalized Multiway Branch Unit for VLIW Microprocessors", IEEE Transactions on Parallel & Distributed Systems, vol. 6, no. , pp. 850-862, August 1995, doi:10.1109/71.406961