<p><it>Abstract—</it>A cross-bridge reconfigurable array of processors is a parallel processing system which has the ability to change dynamically the supported interconnection scheme during the execution of an algorithm. Based on this architecture, several $<tmath>O(1)</tmath>$ time basic operations such as the transpose, the untranspose, the shift, the unshift and the prefix sum of a binary sequence are first proposed. Then, these basic operations can be used to find the $<tmath>k</tmath>$th smallest element of $<tmath>N</tmath>$$<tmath>m</tmath>$ bits unsigned integers in $<tmath>O(m)</tmath>$ time using $<tmath>N</tmath>$ processors and to sort $<tmath>N</tmath>$ data items in $<tmath>O(1)</tmath>$ time using $<tmath>O(N^{{5}\over{3}})</tmath>$ processors instead of using $<tmath>O(N^2)</tmath>$ processors as those proposed by other researchers [<ref type="bib" rid="D05542">2</ref>], [<ref type="bib" rid="D05544">4</ref>], [<ref type="bib" rid="D05548">8</ref>], [<ref type="bib" rid="D055412">12</ref>], [<ref type="bib" rid="D055417">17</ref>], respectively.</p><p><it>Index Terms—</it>Prefix sum, selection, sort, parallel algorithms, cross-bridge, reconfigurable bus, reconfigurable array of processors.</p>