The Community for Technology Leaders
Green Image
Issue No. 03 - March (1995 vol. 6)
ISSN: 1045-9219
pp: 314-328
<p><it>Abstract—</it>It has historically been difficult to distribute a well-aligned hardware clock throughout the physical extent of a synchronous processor. Traditionally, this task has been accomplished by distributing the output of a central oscillator over a tree-like network, with repeaters at necessary intervals. While straightforward in concept, this method suffers from poor reliability, poor scalability and high skew. </p><p>In this paper, we present an alternative approach—<b><it>Distributed Synchronous Clocking</it></b>—that maintains the simplicity of synchronous operation without suffering the drawbacks of centralized clocking. A network of independent oscillators takes the place of the centralized clock source, providing separate clock signals to the physically distant parts of a computing system. A distributed error correction algorithm effects global phase alignment by utilizing local comparisons of neighboring oscillator phase. </p><p>In contrast to centralized clock distribution, distributed clocking has the inherent potential for complete scalability and graceful degradation. However, because oscillator phase is a modular quantity, a naive implementation of distributed synchronous clocking can suffer from <b><it>mode-lock</it></b>—the trapping of local oscillator phase in undesirable stable equilibria where global phase is not aligned [<ref type="bib" rid="D031426">26</ref>]. We present a simple method for eliminating this problem in <math><tmath>$k$</tmath></math>-ary Cartesian meshes and give a proof of its correctness for two-dimensional networks. An electronic implementation is also presented and several engineering issues relating to error tolerance are discussed.</p><p><it>Index Terms—</it>Computer hardware clocking, clock synchronization, distributed clocking, oscillator synchronization, phase-locked loops, mode-locking.</p>

J. Nguyen and G. A. Pratt, "Distributed Synchronous Clocking," in IEEE Transactions on Parallel & Distributed Systems, vol. 6, no. , pp. 314-328, 1995.
90 ms
(Ver 3.3 (11022016))