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Issue No. 12 - December (1994 vol. 5)
ISSN: 1045-9219
pp: 1329-1334
ABSTRACT
<p>On vector supercomputers, vector register processors share a global highly interleavedmemory. In order to optimize memory throughput, a single-instruction, multiple-data(SIMD) synchronization mode may be used on vector sections. We present an interleavedparallel scheme (IPS). Using IPS ensures an equitable distribution of elements on a highly interleaved memory for a wide range of vector strides. Access to memory may beorganized in such a way that conflicts are avoided on memory and on the interconnectionnetwork.</p>
INDEX TERMS
Index Termsvector processor systems; parallel machines; synchronisation; interleaved parallelschemes; vector supercomputers; vector register processors; global highly interleavedmemory; memory throughput; synchronization mode; interconnection network
CITATION
J. Lenfant, A. Seznec, "Interleaved Parallel Schemes", IEEE Transactions on Parallel & Distributed Systems, vol. 5, no. , pp. 1329-1334, December 1994, doi:10.1109/71.334907
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