Issue No. 11 - November (1994 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.329672
<p>A method of reducing the volume of data flowing through the network in a shared memory parallel computer (multiprocessor) is described. The reduction is achieved by difference coding the memory addresses in messages sent between processing elements (PE's) and memories. In an implementation, each PE would store the last address sent to each memory, and vice versa. Messages that would normally contain an address insteadcontain the difference between the address associated with the current and most recentmessages. Trace-driven simulation shows that only 70% or less of traffic volume(including data and overhead) is necessary, even in systems using coherent caches. Thereduction in traffic could result in a lower cost or lower latency network. The cost of thehardware to achieve this is small, and the delay added is insignificant compared tonetwork latency.</p>
Index Termsmultiprocessor interconnection networks; shared memory systems; message passing;storage management; buffer storage; virtual machines; memory traffic; multiprocessors;difference coding; memory addresses; shared memory parallel computer; trace-drivensimulation; traffic volume; coherent cache; lower cost; lower latency network; networklatency; processing elements; memories
D. Koppelman, "Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses," in IEEE Transactions on Parallel & Distributed Systems, vol. 5, no. , pp. 1156-1168, 1994.